Power flow computation using field programmable gate arrays

Power flow computation is ubiquitous in the operation and planning of power systems. Traditional power flow computation is performed using commodity general purpose processors that are commonly found in today's personal computers. These general purpose processors however, are not necessarily designed to provide optimal performance for power flow computation. The goal of these general purpose processors is to provide good performance across a wide range of problems, but not necessarily for all problems. Recently, field programmable gate arrays (FPGA) have been identified as having the capability to compete with these high frequency processors for floating point throughput despite operating at a much lower clock speed. This research presents the methodology used to design an implementation of an FPGA based accelerator for power flow computation that provides increased performance over the standard general purpose processor solution. The design follows a fine-grained study of the sparse LU decomposition of several benchmark power system matrices. Performance results for this hardware design indicate an order of magnitude improvement in solve time compared to a state of the art sparse LU solver package for personal computers. The limitations of fine-grained parallelism are explored and additional performance through higher-level parallelism is also presented.