Mitigating the effects of process variations through microarchitectural techniques

Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. Chip manufacturers push towards smaller transistor dimensions to take advantage of smaller and faster devices as well as higher levels of integration and increased functionality for higher performance. However, this trend also has its own drawbacks. As manufacturing technologies move towards the fundamental limits of CMOS processing, it becomes important to utilize the full potential of the components within the chip. At the same time manufacturability of a single geometry on these chips that is within the required limits are getting increasingly difficult. Also increased device densities manifest itself as higher dynamic power consumption which coupled with increased static power levels results in higher power densities and on-chip temperature levels.;If not handled properly, these effects pose serious threat on chip yield levels, power consumption and reliability. In this research, we explored methodologies to correctly model these effects on current and future processor systems and come up with architecture level solutions that either mitigates these effects or takes advantage of them. We tried to find out effective means to model Process Variations, which becomes more and more important with every technology generation. To address the reducing yield levels due to both performance and power constraints in sub-100nm technologies we proposed several microarchitectural techniques.;We try to achieve dynamic power reduction again by trading-off performance. Faster chips in a batch can be run with a slower clock which would allow the designer to use lower supply voltages for power savings.;A common concept to remedy the effects of variation is speed-binning, by which chips from a single batch are rated by a discrete range of frequencies. We argue that architectural optimizations should consider their effect on the "batch" of microprocessors rather than aiming at increasing the performance of a single processor and propose a new metric called "Batch Performance".;Considering the current trends in processor design, we have also investigated the effects of technology scaling and Process Variations in particular on Multi-Core Processor and 3D fabrication techniques to understand and optimize future microprocessors.