Reliability and performance issues in nanoscale SOI CMOS

This dissertation is an examiner of some emerging reliability and performance issues in nanoscale Silicon on Insulator (SOI) CMOS technologies. Hot Carrier Effects (HCE) in particular, although initially not expected to be a reliability issue for the low operating voltages of modern, nanoscale CMOS technologies, are actually found to persist at or even less than 1.0 V. The possibilities of several low-energy driven mechanisms for hot carrier generation that have been recently discovered and the complicated nature of hot-carrier induced degradation of SOI MOSFETs suggest that a careful interpretation needs to be taken on the hot carrier reliability of deeply scaled SOI MOSFETs.; The influence of the Floating Body Effects (FBEs) in particular on the hot-carrier induced degradation in N-channel SOI MOSFETs is currently not fully understood and several controversial and unexplained results have surfaced in the recent literature. In this dissertation, a series of carefully designed experiments are being conducted to thoroughly examine this issue. The experimental observations show enhanced degradation with increasing FBE strength, establishing the prevailing role of the FBE current enhancement on the degradation over the concurrent lateral electric field reduction. In addition, measurements of the valence band electron tunneling originated substrate currents for both grounded body and body biased transistors (resembling floating body operation) suggests an increasing effectiveness of the associated hot-carrier degradation mechanism for the body biased devices, consistent with the measured degradation results.; With regard to P-channel SOI MOSFETs, we have carried out an investigation of the aging/recovery mechanisms under various stress conditions. It is found that worst case degradation occurs at stress under high gate/high drain bias rather than the conventional low gate/high drain bias. A series of experiments unambiguously demonstrate that this damage is not caused by hot hole injection as it was previously thought and that it is actually due to concurrent Negative Bias Temperature stress, accelerated by device self-heating.; Besides the reliability investigations, this dissertation undertakes an examination of the performance potentials of the Double Gate (DG) SOI structure in novel circuit topologies. The results of these investigations are very timely since DG-SOI MOSFETs are considered to be the most promising device architecture for enabling non-classical, nano-scale CMOS (beyond the 50 nm node). A novel circuit design style is proposed, where a symmetric double gate device featuring a negative threshold voltage (i.e., depletion mode) is used as a load and symmetric double gate devices (inversion mode) serve as the drivers. Using this technique, a basic inverter was designed with better performance compared to "classical" CMOS. This technique was extended to create a robust, self-restoring SOI domino-style logic.