Testing for crosstalk- and bridge-induced delay faults

Process technology advancements are increasing coupling capacitance values and the resulting crosstalk-induced delay. As a result, noise and timing margins are decreasing and circuits' susceptibility to defects is increasing. The population of defects is also changing and the influence of fluctuations of process parameters during manufacturing is becoming more and more important due to process technology advancements.;Due to the above mentioned reasons, crosstalk-induced delay must not only be considered in timing verification but it must also be considered in post-fabrication testing together with realistic populations of manufacturing imperfections and process variations.;This dissertation focuses on testing for crosstalk-induced delay faults in the presence of delay faults caused by defects and process variations. Furthermore, with bridges being the predominant type of manufacturing defects in new technologies, this dissertation also focuses on testing for bridge-induced delay faults in the presence of other delay faults. In the presence of delay faults at unknown locations and of unknown sizes, nominal timing information is not valid. We present timing-independent approaches for testing for crosstalk- and bridge-induced delay faults. Using these approaches, under certain circumstances, tests are generated that guarantee testing for crosstalk- or bridge-induced delay faults. No existing approach generates tests that can provide such a guarantee.;Certain assumptions about the nature of defects and process variations and the resulting delay faults can be exploited in the test methodology that result in higher coverage of crosstalk or bridge sites and also lower test generation and test application costs. These assumptions and their ramifications are also discussed.