Analysis Of Interconnect Signal Integrity Taking Process Fluctuation Into Account

With the rapid development of very large scale integrated circuits manufacturing technology, interconnect process fluctuation has made an important impact on VLSI designing and manufacturing. The impact of interconnect process fluctuation on the interconnect delay and crosstalk noise in VLSI is studied and discussed at the present work. The approximate function relationships are obtained by analyzing the impact of interconnect geometric parameters fluctuation on the interconnect parasitic parameters. On the basis of these studies, the statistical RC interconnect delay model, RLC interconnect delay model and crosstalk noise model are successfully proposed and built respectively. The mathematical expressions of mean and standard deviation of interconnect delay and crosstalk noise can be obtained for given fluctuation range of interconnect technological parameters according to the models proposed in this paper. The computation results show that the time of calculation is greatly shortened with a good calculating precision using the method proposed by author as compared to the widely used Monte Carlo method. The method proposed by this paper will have a potential bright future in the analysis and optimization of VLSI interconnect signal integrity.