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Transport properties of silicon complementary-metal-oxide semiconductor quantum well field-effect transistors

Posted on:2017-12-14Degree:Ph.DType:Dissertation
University:The University of Texas at DallasCandidate:Naquin, Clint AlanFull Text:PDF
GTID:1450390005982835Subject:Condensed matter physics
Abstract/Summary:
Introducing explicit quantum transport into silicon (Si) transistors in a manner compatible with industrial fabrication has proven challenging, yet has the potential to transform the performance horizons of large scale integrated Si devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) n-channel metal-oxide-semiconductor (NMOS) transistors fabricated using industrial silicon complementary MOS processing. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (VG) spacing between NDTCs. The VG spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background.;A folding amplifier frequency multiplier circuit using a single QW NMOS transistor to generate a folded current-voltage transfer function via a NDTC was demonstrated. Time domain data shows frequency doubling in the kHz range at room temperature, and Fourier analysis confirms that the output is dominated by the second harmonic of the input. De-embedding the circuit response characteristics from parasitic cable and contact impedances suggests that in the absence of parasitics the doubling bandwidth could be as high as 10 GHz in a monolithic integrated circuit, limited by the transresistance magnitude of the QW NMOS. This is the first example of a QW device fabricated by mainstream Si CMOS technology being used in a circuit application and establishes the feasibility of scalable CMOS circuits that exploit explicit quantum transport. Ongoing quantum transport simulations based off of the spatial dopant distribution suggests a quasi-parabolic potential profile. Energy spacings between resonant transmission states are not consistent with experimental data, suggesting that either the assumed transport model is incomplete, or scattering mechanisms significantly mix the quasi-bound states and broaden the energy spacings.
Keywords/Search Tags:Transport, Quantum, Silicon
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