| Silicon carbide (SiC) offers great promise in future high power, high voltage, high temperature, high frequency and high radiation environment applications. However, currently one key high power device, SiC bipolar diode, experiences degradation of forward voltage drop during operation, which is the major obstacle in the development of this device. It was reported that the degradation is caused by the propagation of stacking faults in the diode structure. The nucleation sites of stacking faults were studied in this work, and the primary nucleation site was found to be basal plane dislocation (BPD). The BPD density in conventional state-of-the-art SiC epilayers is about 100-500 cm-2, that is, a device with the area of 1 mm x 1 mm will cover at least one BPD. In this work, a novel method was developed to eliminate BPDs during epitaxy, and low BPD density (less than 10 cm-2) and BPD-free SiC epilayers were obtained in our laboratory. The key approach is to subject the SiC substrate to defect preferential etching, followed by conventional epitaxial growth. The creation of BPD etch pits on the substrate surface can greatly enhance the conversion of BPDs to threading edge dislocations during epitaxy, and thus low BPD density and BPD-free epilayers are obtained. It was also demonstrated that SiC bipolar diodes fabricated on such a novel epilayer do not exhibit stacking fault propagation and forward voltage drop degradation during operation. A US provisional patent application was filed based on the above results.; The evolution of dislocations during SiC epitaxial growth is investigated. During conventional SiC epitaxy, 70-90% of BPDs in the substrate are converted to become threading edge dislocations as a result of image force, while the other 10-30% of BPDs will propagate into the epilayer. Prior to this work, the reason why only some BPDs get converted during epitaxy, while others still propagate was not clear in the field. This problem was made clear in this work by using a new approach to track dislocations from SiC epilayer to the substrate.; High-quality (0001) SiC epilayers are obtained in our home-built CVD system at a growth rate up to 25 mum/hr. The typical RMS roughness of the 10-30 mum thick epilayers is about 0.6 nm. The net doping concentration (Nd-Na) of the epilayers is controlled to be less than 1015 cm-3 n-type by adjusting the C/Si ratio. Thick epilayers up to 80 mum, and large diameter epilayers up to 2-inch are also obtained. |
