Fully Integrated On-Chip Switched Capacitor DC-DC Converters for Battery-Powered Mixed-Signal SoCs

In this dissertation, a new 4-to-3 step-down topology for on-chip SC DC-DC converters, which efficiency is less sensitive to increasing bottom-plate capacitance ratio (alpha) than the conventional topologies, is proposed. In addition, two different implementations of on-chip SC DC-DC converters using the new 4-to-3 step-down topology are presented.;For the first implementation, the on-chip SC DC-DC converter supports a programmable regulated load voltage ranging from 2.6V to 3.2V out of 5V input power supply. Only MOS capacitors (2.7fF/um2, alpha=6.5%; alphais the bottom-plate capacitance ratio) are used as flying capacitors (900pF) and load capacitor (400pF) for the minimum area/cost. To maximize the load current driving capability while minimizing the bottom-plate capacitance loss, the proposed 4-to-3 step-down topology utilizes two conventional 2-to-1 step-down topologies; each of them (2-to-1_up and 2-to-1_dw) has a different flying capacitance. As the control circuits operates at a low power supply (1.6V), which is provided by a small internal LDO connected to the internal load voltage (VL') from the 2-to-1_dw, and the internal load voltage (VL') is used to generate low swing level-shifted gate-driving signals, the proposed implementation reduces control circuit and switching losses as well. The proposed converter achieves the peak efficiency of 74% while it delivers the load current between 1mA and 10mA. 10-phase interleaving technique enables the maximum voltage ripple in the load voltage to be less than 1% of the average load voltage ( 3.2V).;For the second implementation, the on-chip SC DC-DC converter that supports two regulated load voltages (2.2V and 3.2V) from 5V input supply and delivers the maximum load currents up to 8mA is proposed. The entire converter utilizes two conventional 2-to-1 converter blocks. The upper output voltage (3.2V) is generated from the 2-to-1_up converter and the lower output voltage (2.2V) is generated from 2-to-1_dw converter. Since the efficiency of the 2-to-1_up converter is less sensitive to increasing alpha, it is implemented with MOS capacitors while the bottom-plate capacitance loss sensitive 2-to-1_dw converter is implemented with MIM capacitors (1fF/um2, alpha=2.5%). The proposed implementation saves the area and quiescent currents for the control blocks since each converter block shares required analog and digital control circuits. Over the wide output power ranges from 5.4mW to 43.2mW, the converter achieves the average efficiency of 70.0% and the peak efficiency of 71.4%. 10-phase interleaving technique enables the maximum voltage ripples in the both loads less than 1% of the load voltages.;The two SC DC-DC converters presented in this dissertation are designed and simulated using high-voltage 0.35um BCDMOS technology and demonstrate higher than 70% peak efficiencies. Efficiencies of the both converters are less sensitive to increasing alpha than the conventional SC topologies. This work shows that the on-chip SC DC-DC converters can outperform the linear regulators in terms of efficiency, at least 10% higher efficiency, with a little expense of area/cost. Since the merits of the SC converters have be increasing with technology scaling, SC DC-DC converters are promising alternatives of linear regulators for low power (<50mW) on-chip DC-DC converters's applications in the modern portable SoCs. (Abstract shortened by UMI.).