Design And Simulation Of LDO Biased A High Power Supply Rejection Ratio Without An Off-chip Capacitance

With the rapid development of 5G communication technology,power management has gradually become an area of great concern.Low-dropout linear regulator（LDO）,as an important power management chip,stands out among analog power ICs with its low noise,low cost,and high efficiency.In order to ensure the stability of system,the traditional LDO uses a large-capacity off-chip capacitor with equivalent series resistance which can generate a zero point of left half-plane at the output to offset the secondary point.However,it increases PCB area and component costs,and makes it difficult to apply to highly integrated design for SoC.Thus,no off-chip capacitor LDO has gradually become a research hotspot today.Firstly,this paper uses high-order curvature compensation technology and a full CMOS current reference circuit to improve the temperature characteristics of the bandgap reference voltage and reference current.Therefore,the accuracy of the LDO is guaranteed;Secondly,the gate-drain parasitic capacitances C_gd,pow（pF level）of the power transistor and compensation capacitance C_m are used to implement the nested Miller compensation,and the two non-dominant poles at the output of the second-and third-stage amplifiers are pushed out of the unit gain bandwidth（UGB）to guarantee the stability of loop;Then,the adaptive bias circuit is used to duplicate the load current in order to provide adaptive bias for the error amplifier.At the same time,in order to reduce the overshoot voltage during fast load jump,the transient enhancement circuit is used to improve the current efficiency of the LDO under light load and the transient response characteristics under heavy load;Finally,the enhancement circuit for PSRR is used to push the secondary pole generated at the gate of the power transistor to a higher frequency band,which expands the power supply rejection ratio bandwidth and increases PSRR in the middle and high frequency bands.In the meantime,over-temperature,over-current and short-circuit protection circuit are integrated to extend the lifetime of the device and ensure the safety of circuit.The LDO biased high power supply rejection ratio in this paper is designed by using TSMC0.18μm standard CMOS process.The overall simulation achieves the following performance indicators:when the input voltage is 1.4～2V,the output voltage is stable at 1.2V and the load current range is 10μA～100m A;the maximum temperature coefficient of the output voltage is 3.723 ppm/℃,and the maximum load regulation and linear regulation are 6.1μV/m A and0.525m V/V,respectively.PSRR simulation at 1KHz and 100KHz,the maximum power supply rejection ratios are 96.82d B and 58.87d B,respectively,which means that LDO has good power supply rejection characteristics;when the load jumps between no-load and full-load,the maximum positive and negative overshoot voltages at the LDO output are 70m V and 62m V,respectively,and the corresponding recovery time are 7.55μs and 8.28μs.Thus LDO has good load transient response.The LDO biased high power supply rejection ratio in this paper has universality in circuit structure and has reference and practical significance.