| The performance of main memory has always been a critical factor in overall system performance, and its importance is growing for multi-core and future many-core systems. To boost memory throughput under saturating access latency, modern DRAM systems leverage parallel requests to increasing number of DRAM banks/channels. However, the overall system performance cannot benefit from increasing hardware parallelism without parallel access patterns to these banks/channels. It has been shown that substantial improvements in memory performance can be achieved by improving the parallelism of the access patterns through enhancing software and hardware constructs. On the other hand, increasing DRAM utilization has the disadvantage of higher power consumption and operating temperatures in DRAM systems. Traditional DRAM power and thermal management techniques, which either require long DRAM idle periods or incur unnecessary performance, are not suitable for high performance systems.;To systematically address performance and thermal challenges in high performance DRAM systems, we proposed architectural and OS-level optimizations to increase memory level parallelism and improve the power and thermal efficiency of DRAM systems. Specifically, we proposed Page Hit Aware Write Buffer (PHA-WB) to improve the DRAM power efficiency by reducing row buffer miss rate. PHA-WB intelligently buffers write operations that miss the row buffer, and thus reduces power wastes incurred by redundant DRAM activate operations.;To maximize thermal power envelope under limited cooling resource, we propose Temperature Aware Least Recently Used (TA-LRU) cache replacement policy and Temperature Aware Page Allocation (TA-PA), which increase DRAM cooling efficiency by minimizing temperature variations among different DRAM chips. With minimal modifications in the DRAM rank organizations, TA-PA and TA-LRU generate uneven DRAM traffic to DRAM ranks based on their thermal behavior, and thus relieve cooling pressure on overheating DRAM chips.;Finally, we proposed Parallelism Aware Migration (PAM) to improve potential memory level parallelism in the DRAM access patterns. PAM utilizes hardware performance counters to monitor conflicts among pages in each memory channel. Pages that experience anomalous conflict in its residential channel are migrated to channels with less confliction. |
