| The remarcable performance of nitride based heterostructure field effect transistors (HFETs) is well-known. Their high heterointerface electron populations, high values of the mobility and saturation velocity, as well as their wide bandgap that allows for high elevated temperatures, make these devices very attractive for high power, high speed applications.; Up to recent times there was a serious limitation in the performance of these devices referred to as current collapse. Current collapse manifests itself in a drastic decrease of the device peak current after a gate voltage close to the device threshold is applied. Due to this effect under large input signals the device peak current is usually 3 to 5 times less than that expected from DC characteristics.; The mechanism of current collapse is the focus of this work. It is concluded that there are several locations for traps responsible for the phenomena. By the improvement and optimization of the device processing, the collapse related to the surface and barrier is reduced. Then, several methods to eliminate the buffer-related collapse are successfully developed. These include double the heterostructure approach, the PALE buffer layer growth technique, and the field plate design. Collapse-free HFETs with high output RF powers up to 9 W/mm are obtained by each method of current collapse elimination.; Experimentally proven analytical models for each method of current collapse elimination are presented; these models help to optimize the devices for the best DC and RF performance. |
