A domain-specific cell based ASIC design methodology for digital signal processing applications

Research has shown that standard cell based application-specific integrated circuit (ASIC) designs, or standard ASICs, usually work 5 to 8 times slower than fully custom designed ASICs, or full-custom ASICs. Furthermore, full-custom ASICs have more compacted final layouts, with lower power consumptions, than standard ASICs. On the other hand, automatic standard cell based ASIC design methodology offers many advantages over full-custom design methodology, such as fast turn-around time, less design resource requirement, higher productivity and thus lower prices. For all these reasons, standard ASICs are still attractive today. Improving the design quality, while still preserving its low design time, is the primary research goal in this project.; An innovative domain-specific cell based ASIC design flow is described in this dissertation, with the purpose of narrowing the performance gap between the full-custom ASIC design and conventional standard ASIC design methodologies. This design flow improves the design performance and still preserves the efficiency of the standard ASIC design flow. Targeting on digital signal processing applications, a domain-specific cell library is provided to augment a standard cell library. Experimental results of designing macros such as FFT, FIR etc. are shown in this dissertation. Based on this methodology a 64-tap FFT can achieve up to 26X performance improvement, using the Power x Delay x Area (PDA) criteria, over the conventionally designed ASIC.