Design and implementation of advanced encryption standard in FPGA and 0.18 micron CMOS-based ASIC

Rijndael is the new Advanced Encryption Standard (AES) that was chosen by the American National Institute of Standards and Technology (NIST) in October 2000. The ever growing speed of communication networks, combined with the high-volume of traffic and the need for physical security, creates a large demand for efficient implementations of AES in hardware. This thesis focuses on the design and implementation of AES using reconfigurable hardware technology based on Field Programmable Gate Arrays (FPGAs) and in a 0.18-Micron semi-custom Application Specific Integrated Circuit (ASIC). Various design circuits for iterative architecture were investigated when implementing the algorithm in a Xilinx Virtex FPGA, and the en_decryption algorithm was implemented as an ASIC using 0.18 um CMOS standard cell library (black-box library) provided through TSMC (TAIWAN Semiconductor Manufactory Company). Our investigation shows for FPGA implementations a maximum encryption speed of 528 Mbit/s can be achieved, and for ASIC implementation the throughput can be more than 1 Gbit/s.