| Traditional testing research for Very Large Scale Integrated (VLSI) circuits has been confined to the use of serial scan test architecture whose origin lies in keeping the hardware overhead low. However, there has been a paradigm shift in the cost factor--the transistor cost has been dropping exponentially whereas the test cost is starting to increase. Thus, it is believed that adding marginally more hardware is acceptable provided the test cost can be reduced considerably.; This dissertation takes such a view of testing and rejuvenates the random access scan as a design for testability method that addresses three main limitations of the traditional serial scan, namely, (1) test power consumption, (2) test application time, and (3) test data volume. This dissertation develops novel random access scan test architecture called Progressive Random Access Scan (PRAS) and comprehensive test methods that include generalization of PRAS architecture, test vector modification, test vector generation and test application for the proposed PRAS architecture.; The performance of PRAS architecture, together with proposed vector modification/generation methods, is evaluated with extensive experiments on both benchmark and large industrial circuits. The experimental results verify that the three problems stated above are simultaneously and dramatically reduced with only marginal increase in the design for testability circuit. In addition, future research directions to address various other test problems, such as delay fault testing and fault diagnosis using PRAS architecture are suggested. |
