Extended Compatibilities For Multiple Scan Tree Construction Of Digital Circuits Test

In recent decades, with the rapid development of very large scale integration (VLSI) technique, the density of transistors in integrated circuits (ICs) increases dramatically, hence the testing is becoming a huge challenge and a research hot point as well. Full scan-based design is one of the most popular DFT techniques and it is widely used in VLSI circuits or in system-on-chip (SOC) cores. This DFT technique enhances all flip-flops of a circuit to scan cells, and concatenates all scan cells to one or more scan chains. Its test application time depends on the length of the longest scan chain. Unfortunately, although full scan-based design reduces test generation complexity drastically and provides high fault coverage by transforming a sequential circuit to its combinational part in test mode, the test cost including test application time, test data volume and test power is quit high, and it increases the cost of automatic test equipment (ATE).Extended compatibilities scan tree technique, employing logic NOT and XOR functions, reduces test application time, test data volume and average test power drastically by shifting the same test values into(out from) the compatible scan flip-flops simultaneously. However, there does not exist a literature about multiple scan tree construction of extended compatibilities. Nevertheless, in the practical test a circuit under test usually has more scan inputs. The test application time is reduced to 1/N of that with single scan-input when the circuits under test (CUTs) have N scan inputs.This thesis proposes a novel construction for test application time, test data volume and test power reduction. In this construction, the CUTs have multiple scan inputs. We construct multiple extended compatibilities scan trees for the CUTs. Experimental results show that our approach is more effective to achieve short test application time and low average power dissipation compared with the single scan tree design with extended compatibilities. For ISCAS'89 benchmark circuits, the test application time of our approach is reduced up to 52.4%, and the average power is reduced up to 60.8%, when the number of scan inputs is two.