Design approaches for nanoscale logic and memory architectures

In recent years, novel nanotechnology has been considered as an eventual replacement or extension to existing microelectronic technologies (e.g., CMOS) as they migrate to smaller scales. This work considers the versatility and scope of nanoscale devices, in particular the memristor, when employed in different nanoelectronic and hybrid CMOS/Nano circuits to realize several flavors of memory and logic implementations. In particular, this work proposes three novel hybrid CMOS/Nano memory and logic systems. The first system put forth is a high density hybrid CMOS/Nano field programmable gate array (FPGA) built from programmable majority logic arrays (PMLA). The second system is an innovative non-volatile multi-level memory built with memristive devices that are used as memory elements. The third system is a trainable threshold gate array (TTGA) that utilizes memristors as synapses in trainable artificial neural networks. For all the aforementioned systems, the methodologies by which the nanoscale devices and circuits are modeled, designed and employed to realize desired system functionality are detailed.