| In this dissertation, combined numerical (Finite Element Method) and experimental efforts were undertaken to study thermo-mechanical behavior in microelectronic devices. Interconnects, including chip-level metallization and package-level solder joints, are used to join many of the circuit parts in modern equipment. The dissertation is structured into six independent studies after the introductory chapter. The first two studies focus on thermo-mechanical fatigue of solder joints. Thermo-mechanical fatigue, in the form of damage along a microstructurally coarsened region in tin-lead solder, is analyzed along with the effects of intermetallic morphology. Also, lap-shear testing is modeled to characterize the joint and to investigate the validity of experimental data from different solder and substrate geometries. In the third study, the effects of pre-machined holes on strain localization and overall ductility in bulk eutectic tin-lead alloy is examined. Finite element analyses, taking into account the viscoplastic response, were carried out to provide a mechanistic rationale to corroborate the experimental findings. The fourth study concerns chip-level copper interconnects. Various combinations of oxide and polymer-based low-k dielectric schemes, with and without the thin barrier layers surrounding the Cu line, are considered. Attention is devoted to the thermal stress and strain fields and their dependency on material properties, geometry, and modeling details. This study is followed by a chapter on atomistics of interface-mediated plasticity in thin metallic films. The objective is to gain fundamental insight into the underlying mechanisms affecting the mechanical response of nanoscale thin films. The final study investigates the effect of microstructural heterogeneity on indentation response, for the purpose of raising awareness of the uncertainties involved in applying indentation techniques in probing mechanical properties of miniaturized devices. |
