High-performance arithmetic for division and the elementary functions

Many numerically intensive applications, such as signal processing, require rapid execution of arithmetic operations. The computational demand goes beyond fast addition and multiplication. Support for high-performance divide and the elementary functions is becoming increasingly necessary. The architecture of a general purpose arithmetic unit capable of such support is proposed and analyzed. The arithmetic unit is based on parallel functional computation. Functions such as square root, inverse square root, exponential, logarithm, and trigonometric functions may be expressed as a Taylor series expansion suitable for evaluation by the proposed arithmetic unit.; This proposed arithmetic unit provides rapid convergence based on higher-order series expansion techniques. The architecture provides fast and efficient function evaluation while allowing high throughput. The arithmetic unit achieves fast computation by using parallel squaring, cubing, and powering units. These units compute the higher-order terms significantly faster than the traditional approach of serial multiplication. Furthermore, all of the terms are computed concurrently, further reducing the latency. Significant hardware reductions are proposed to minimize the area, latency and power consumption of the computation. Finally, the arithmetic unit computes the result directly without iteration, therefore, allowing for a fully pipelineable implementation.; The design space for IEEE single and double precision floating point numbers has been studied for division, square root, and inverse square root. All IEEE rounding modes for division are supported by the arithmetic unit. Area and latency comparisons between the proposed arithmetic unit and other state-of-the-art implementations are presented.; The proposed arithmetic unit pushes the area-latency boundary of the design space and provides a means to achieve the computational demands of numerically intensive applications.