| In this research, the packaging process-induced stresses in flip chip assemblies and their reliability were investigated using experimental and analytical approaches. A capillary flow flip chip underfill process and an innovative dispenseless fluxing no flow underfill process were developed for the fine-pitch high-I/O count microsystems. The packaging process-induced stresses in the flip chip microsystems were experimentally characterized by the piezoresistive stress sensors at each packaging process phase. The in-situ substrate warpage was measured by a shadow moiré system. A power cycling accelerated life test system was developed to investigate the interconnection field reliability of the flip chip microsystems. The failure modes were validated by scanning acoustic microscopy (SAM), X-ray, cross-section analysis, and scanning electron microscopy (SEM). A physics-based analytical model was also developed to predict the process-induced stresses in the flip chip microsystems, the substrate warpage, and the field reliability of the interconnections. Virtual design optimization and design for field reliability were achieved by utilizing this validated model. |
