Research On Reliability For Flip-chip Package And Through Silicon Via (TSV) In3D Package

Electronic products’ reliability largely depends on their package reliability. Withelectronic products’rapid development to be of more I/Os and higher density, the requirementfor packaging reliability has been more strict. This thesis mainly focuses on electronicpackages’ reliability, especially, reliability for flip-chip package and TSV(through silicon via),which is the key technology to realize3D interconnection, in3D package. Because of itsexcellent performance in high frequency and almost ideal packaging density, flip-chippackage has attracted more and more attention and has the great potential to be one of themain packaging modes in the future. TSV has been seen as one of the most critical technologyto realize3D interconnect and its realiability can directly affect realiability of the whole3Dpackaging products. Structural optimization design for TSV can provide guidance forprocessing and enhance its mechanical reliability. Based on the finite element method, maincontents of this thesis are as follows:（1） Propagation behavior of interfacial delamination at chip/underfill interface inhorizontal and vertical direction are respectively studied. It turns out that it is more likely fordelamination in horizonal direction to take place and after the interfacial delaminationpropagates a certain distance, that in vertical direction begins to initiate; as for interfacialdelamination in horizontal direction, the mode of its driving force is studied, the results showthat when delamination initiates or crack is short, shearing stress plays the dominant role,however, when it propagates a relative long distance, opening stress makes the biggercontribution.（2） Effects of defects induced by underfill filling process and delamination alonghorizonal interface between chip and underfill on solder joints’ life are respectively analyzedand compared. It indicates that interfacial delamination has a bigger impact on solder joints’reliability and once unstable propagation happened, the whole flip-chip package may fail towork.（3） Life prediction for solder joints in flip-chip package is studied, which iscomposed of constitutive model selection for leadfree solder and comparing of different life prediction models. It is found that the life prediction models based on frature parameter andplastic strain respectively could lead to big error, and the model based on creep could predictsolder’s lifespan which could be very close to experimental results. Therefore, creep can beregarded as the main deformation mechanism when flip-chip works or undergoes thermalcycling. In addition, the creep deformation is mainly concentrated in the second stage (creepdeformation is composed of three stages in total) and the hyperbolic-sine law can describeSn-Ag-Cu solder’s creep deformation when flip-chip works.（4） Thermo-mechanical reliability design for the TSV stacked-dies3D package isimplemented and a new TSV structure is introduced and thermo-mechanical reliabilitycomparing between the new structure and the traditional copper-filled structure is made.Through combinating the design of experiment (DoE) with the finite element analysis, effectsof parameters, such as via pitch, copper via diameter, chip thickness, solder diameter andYoung’s Modulus of underfill, on TSV’s reliability, it is found that copper via’s diameter andYoung’s Modulus of underfill have the greatest effect on TSV’s reliability and the reliabilitydecreases with the increase of copper via’s diameter and Young’s Modulus. What’s more,compared with traditional copper-filled TSV structure, the new one has betterthermo-mechanical reliability.