Phase realignment and phase noise suppression in PLLs and DLLs

Ring oscillators are widely used in clock generation for digital systems and low-performance communication applications due to their simplicity, wide tuning range and ease of integration. However, the excessive noise in ring oscillators makes them less desirable for high-performance communication systems. This dissertation presents two applications where the advantages of ring oscillators are exploited while their disadvantages are addressed using novel system topologies.; In Chapter 1, a simple, yet accurate model is presented to describe the injection locking behavior in a novel clock distribution scheme using a network of strongly coupled oscillators. The model parameters are conceptually simple and can be easily obtained through transistor-level simulation. The proposed model is capable of accurately describing the injection-locking behavior among strongly coupled ring oscillators.; In conventional integer-N Phase-Locked Loops (PLL), the attenuation to the Voltage Controlled Oscillator (VCO) phase noise is limited by the system stability requirement, which prevents the use of ring oscillator based VCOs due to their excessive close-in phase noise. To overcome this conventional barrier, a clean reference pulse can be injected periodically into the VCO so as to reset the phase error and thereby suppress the noise memory. This technique, referred to as "phase realignment", can result in significant attenuation of the in-band phase noise. Chapter 2 presents the prototype of such a scheme and, when it is enabled, a peak spot phase noise reduction of 10 dB is observed compared with the conventional approach. In addition, a theoretical model is developed and used to improve the performance of the next-generation version of the prototype as presented in Chapter 3. Specifically, a novel ring VCO topology is developed which is not only optimized for the best phase realignment, but also designed to attenuate the 1/f noise using the switched biasing technique. A peak spot phase noise of 21.5 dB is observed when both noise attenuation schemes are enabled. Design guidelines for optimization of the loop parameters are derived from the theory and are closely supported by the measurement.