Implementation and improvement for RF low-noise amplifiers in conventional CMOS technologies

The feasibility of implementing CMOS low noise amplifiers (LNAs) fabricated using a digital CMOS process is demonstrated. Traditionally, CMOS implementations of RF circuits have been inferior to those fabricated in other technologies. The recent advances in silicon MOSFET technology have opened up the possibility of implementing high performance RF CMOS circuits.;Using a cascode and common-source (CS) amplifiers, an LNA has been demonstrated in a 0.8-mum digital CMOS process. The noise figure (NF) and power gain (S21) were 4.5 dB and 13.8 dB at 820 MHz with 11 mA do bias. This was one of the first CMOS LNAs with integrated inductors. The gain was reasonable for typical ISM band applications, while NF needed to be improved. A revised LNA with input stage noise reduced and larger area substrate contacts showed NF of 2.9 dB and S21 of 16.5 dB. Two low-capacitance ESD diode structures were implemented to protect against 1500-V ESD events. The addition of the ESD structures resulted in NF and S21 degraded by 0.2 dB and 0.3 dB, respectively. This was the first CMOS LNA to achieve NF below 3.0 dB and incorporate ESD structures.;4-GHz tuned amplifiers in a 0.1-mum CMOS technology on bulk, SOI, and SOS substrates have been implemented. At VDD = 1.5 V, S21 of 14 dB at 4.1 GHz, 11 dB at 4.3 GHz, and 12.5 dB at 4.6 GHz were measured for the bulk, SOI, and SOS amplifiers, respectively. Measured NFs at 4 GHz were 5.5, 5.8, and 4.3 dB for the bulk, SOI, and SOS amplifiers. When reported, the 4-GHz bulk amplifier had the highest resonance frequency among the bulk CMOS amplifiers. The study of isolation characteristics using a substrate impedance model demonstrated the detrimental effect of SOI and SOS substrates at high frequencies.;A method using an inductor and a capacitive transformer to increase power gain has been established. The output power of a circuit using an inductor with L = 9.83 nH, QL = 12.6 and CL = 0.23 pF, and a capacitive transformer was 10 dB higher than the circuit using an RF choke. This capability can make a single-stage RF CMOS LNA possible with lower power consumption.;Finally, a new single-stage CG LNA structure using a negative conductance circuit and a capacitive transformer was developed, where the higher g m of the CG amplifier can improve NF and S21. Using a 0.25-mum CMOS process, the new CG LNA was designed which has NF of 1.0 dB and S 11 of -19 dB at 2.4 GHz. S21, S12 and S 22 are 12.2 dB, -21 dB, and -21.2 dB, respectively. From the characterization, it was shown that a considerable amount of substrate resistance in a MOSFET model exists and can significantly degrade the CG LNA performance.