An integrated framework for yield learning in semiconductor manufacturing

This research concerns an innovative approach to the strategic problem of yield enhancement that arises in the semiconductor industry. Specifically, we develop an integrated framework for the modeling and analysis of yield learning in the wafer fabrication process. The objective is to provide a prescriptive solution to achieve fast learning through (1) the (operational) implementation of a novel combined defect inspection and classification methodology, (2) an efficient (tactical) allocation of tool and engineering resources, and (3) the optimal (strategic) deployment of inspection and information technology over the process/product life cycle.; In the first excursion reduction model, we optimize the in-line wafer inspection sampling which is one of the fundamental activities for yield enhancement. The production system is modeled as a partially observable Markov process which can be in either an in-control state or an out-of-control (excursion) state. Standard control chart techniques are used to monitor the process. Since excursions create opportunities for learning, our model echoes the icon that defects (excursions) are treasures . We incorporate the effects of false alarms, queueing delays and most significantly, the cycle-time elasticity of price into the model. Our results show that for a given level of resource, the optimal inspection decrease with the cycle-time elasticity of price. As the cycle-time elasticity of price approaches infinity, the value of inspection sampling is reduced drastically. This accounts for the slogans such as zero defect metrology and statement that inspection is a non-value added step---an observation that current literature on inspection sampling has failed to explain.; In a second model, we formulate a micro-model of defect classification sampling and multi-class SPC chart at one layer (or stage) of multi-stage wafer fabrication processes and analyze its performance with respect to the resulting b risk and costs. A model that incorporates the observation errors occurring due to imperfect classification of defects on wafer is also solved. We show that the optimal control limit is of the threshold type in the two dimensional space of the observed total defect count and killer defect estimates. We compare the effectiveness of SPC in different scenarios and policies. The complete characterization of b risks as a function of the defect sampling fraction and defect classification accuracy for a given allowable a enables the optimization of defect sampling fraction with respect to any higher level objective function.; The third model concerns the optimization of the wafer inspection strategy in multiple periods with learning effects. We take a finite horizon dynamic programming approach to determine the amount of sampling and the level of resources to invest such that the net present value of the average operating costs is minimized. The results demonstrate that a myopic producer will choose to acquire the inspection resource gradually according to the production ramp schedule, while a global optimizer invests on resources in the beginning of production and uses the excess capacity to boost yield early. With a high cycle-time elasticity product line, a producer choose to invest on more tool capacity and allow the tool to operate at a lower utilization level such that the cycle time will suffer less; furthermore, the reduction in the amount of sampling is also more dramatic than the firm with a lower cycle-time elasticity of price. With assignments of terminal costs of each state, this model can account for why Korean semiconductor companies' investment on yield enhancement resources is much more aggressive than other companies. Our model shows that a firm would choose to invest more on the yield enhancement resources with the anticipation of dumping charges by the U.S.