High-speed image acquisition system for focal-plane arrays

Imaging detector arrays and image processing circuits are critical components in many consumer, industrial, and military focal plane imaging array systems. System specifications emphasize different aspects of imaging array technology, including high frame rate, large array size, high fill factor, and high pixel resolution. The combination of higher resolution with a larger number of pixels has resulted in data rates that can not be transmitted off of the imaging array through a one-port readout system. This data bottleneck is exacerbated when the application demands high frame rates, which further challenge the data transfer rate off of the imaging array.; This dissertation evaluates the potential for the real time utilization of high frame rate image sequences using a fully parallel readout system. Multiple readout architectures for high frame rate imaging are compared. The application domain for a fully parallel readout system is identified, and the design for a fully parallel, monolithically integrated smart CMOS focal plane array is presented. This focal plane image processing chip, with an 8 x 8 array of Si CMOS detectors which each have a dedicated on-chip current input first order sigma delta analog to digital converter front end, has been fabricated, and test results for uniformity, linearity and modulation noise are presented.