Low-power low-voltage analog-to-digital conversion techniques using pipelined architectures

With a recent boom of portable applications from camcorders to wireless personal communication devices, power reduction in high speed A/D converters is becoming increasingly important to minimize battery drain for longer device operating hours. Low voltage operation is another key requirement for these A/D converters in order to be integrated in larger mixed signal IC's containing mostly digital blocks from DSP and control.;The main objective of the research is to examine the fundamental limitations to high speed CMOS A/D converters and to develop techniques to reduce power dissipation and to allow low voltage operation in a pipeline A/D converter architecture. Proposed circuit techniques for low power consumption are the use of fully dynamic comparators that dissipate no DC power, made possible by the digital correction within the pipeline, and optimum scaling of switched capacitor circuits down the pipeline. Also, to be compatible with low voltage mixed-signal system environments, a switched capacitor circuit in each pipeline stage is implemented and operated at 3.3V with a new high speed low voltage operational amplifier, and dynamic gate voltage boosting technique is used to operate transmission gates with full analog voltage switching capability on a 3.3V supply.;To verify the effectiveness of the proposed techniques, a 10bit 20MS/s pipeline A/D converter is designed and fabricated in 1.2...