A 13-bit pipelined reference refreshing cyclic analog-to-digital converter

A 13-bit pipelined reference refreshing cyclic analog-to-digital (A/D) converter using switched-capacitor techniques is presented. Compared with the reference refreshing cyclic A/D conversion technique (2), the pipelined reference refreshing cyclic A/D conversion provides a speed up by a factor of three. This is achieved by the use of pipelined conversion strategy, where only 22 redundant capacitors and 66 switches are added, nevertheless increase the die area only about 13%.;An experimental prototype for the operational amplifier has been designed and simulated by using SPICE. The simulation results illustrated a 91.3 dB open-loop gain, 30.6 MHz unity-gain frequency and a common-mode rejection ratio of 156.75 dB. A test chip for the operational amplifier was fabricated by MOSIS and evaluated. The pipelined reference refreshing cyclic A/D converter was then built on breadboard by using three fabricated operational amplifiers, CMOS control logic, analog switches and 1000 pF storage capacitors. The test data shows that the pipelined reference refreshing cyclic A/D converter performs as an 8-bit converter with differential and integral nonlinearity less...