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The Influence of Impurities and Metallic Capping Layers on the Microstructure of Copper Interconnects

Posted on:2015-10-30Degree:Ph.DType:Dissertation
University:State University of New York at AlbanyCandidate:Rizzolo, MichaelFull Text:PDF
GTID:1471390017488826Subject:Nanotechnology
Abstract/Summary:
As copper interconnects have scaled to ever smaller dimensions on semiconductor devices, the microstructure has become increasingly detrimental for performance and reliability. Small grains persist in interconnects despite annealing at high temperatures, leading to higher line resistance and more frequent electromigration-induced failures. Conventionally, it was believed that impurities from the electrodeposition pinned grain growth, but limitations in analytical techniques meant the effect was inferred rather than observed.;Recent advances in analytical techniques, however, have enabled this work to quantify impurity content, location, and diffusion in relation to microstructural changes in electroplated copper. Surface segregation of impurities during the initial burst of grain growth was investigated. After no surface segregation was observed, a microfluidic plating cell was constructed to plate multilayer films with regions of intentionally high and low impurity concentrations to determine if grain growth could be pinned by the presence of impurities; it was not.;An alternate mechanism for grain boundary pinning based on the texture of the seed layer is proposed, supported by time-resolved transmission electron microscopy and transmission electron backscatter diffraction data. The suggested model posits that the seed in narrow features has no preferred orientation, which results in rapid nucleation of subsurface grains in trench regions prior to recrystallization from the overburden down. These rapidly growing grains are able to block off several trenches from the larger overburden grains, inhibiting grain growth in narrow features.;With this knowledge in hand, metallic capping layers were employed to address the problematic microstructure in 70nm lines. The capping layers (chromium, nickel, zinc, and tin) were plated on the copper overburden prior to annealing to manipulate the stress gradient and microstructural development during annealing. It appeared that regardless of as-plated stress, nickel capping altered the recrystallized texture of the copper over patterned features. The nickel capping also caused a 2x increase in the number of advantageous 'bamboo' grains that span the entire trench, which effectively block electromigration pathways. These data provides a more fundamental understanding of manipulating the microstructure in copper interconnects using pre-anneal capping layers, and demonstrates a strategy to improve the microstructure beyond the capabilities of simple annealing.
Keywords/Search Tags:Copper, Microstructure, Capping layers, Interconnects, Impurities, Grain growth, Annealing
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