OPTIMIZATION OF DISCRETE HIGH POWER MOS TRANSISTORS

A properly designed and fabricated discrete MOS power transistor has a minimum on-resistance per unit area when operated in the forward direction, and a breakdown voltage approaching plane breakdown with no sudden decrease in breakdown voltage or "latchback" when reverse voltage is applied. This work optimizes the performance of MOS transistors by considering three smaller problems. (1) Maximization of the breakdown voltage of planar MOS transistors for a given epitaxial layer resistivity using planar techniques. (2) Determination of the causes of latchback in the reverse breakdown of power MOS transistors, and modifications to device structure that prevent this latchback. (3) Determination of the fabrication technology and device geometry that gives a minimum on-resistance for a given chip area and breakdown voltage when the MOS transistor is fully conducting. All three problems are experimentally and theoretically investigated in lateral DMOS (LDMOS), vertical DMOS (VDMOS) and V-groove MOS (VMOS) power transistors.; Maximization of the reverse breakdown voltage was investigated using two planar field-shaping techniques--the use of a field plate or the use of field limiting rings--at the perimeter of the body junction. Experiments showed that for less than 250 volts, field plates are more efficient for increasing the breakdown voltage, while field limiting rings are more efficient above 250 volts.; The reverse breakdown characteristics of all three power transistor structures were found to exhibit latchback when the reverse current exceeded a limit. The latchback behavior was found to be caused by lateral current flow through the body region of the MOS transistor. This current flow biases the parasitic NPN transistor that is intrinsic to all DMOS structures in the active region, decreasing the breakdown voltage from the BV(,DSS) of the MOS transistor to the BV(,CEO) of the bipolar transistor. This latchback can be prevented by the addition of a diode with a slightly lower breakdown voltage that diverts the reverse breakdown current around the active region of the MOSFET without altering the normal operation of the MOS transistor in the forward direction.; Investigation to determine which of the transistor structures has the lowest on-resistance as a function of breakdown voltage showed that two device types, LDMOS and VDMOS transistors, provide minimum on-resistance over the entire range of breakdown voltages. The LDMOS structure gives the lowest on-resistance for breakdown voltages of less than 30 to 40 volts, while the VDMOS transistor structure gives the lowest on-resistance for breakdown voltages greater than 30 to 40 volts.