Three-dimensional Integration Of Silicon Nanowires And Ultralow Temperature Growth Technology

As the fundamental logic unit for integrated circuits,the field effect transistors(FETs)are mainly constructed via top-down lithography and etching approaches.Now,the FET channels are evolving from planar architecture into three-dimensional(3D)fin and nanowire(NW)geometries,where the advanced gate-all-around FET(GAA-FET)architecture,fabricated by using sophisticated Extreme Ultra-violet(EUV)lithography,allows for a greatly enhanced electrostatic channel control and reduced short-channel effect.On the other hand,the self-assembly method offers a more convenient and versatile strategy to synthesize high quality ultrathin Si NWs with diameter down to <10 nm.Based on the self-assembly Si NWs,various electronic device prototypes have been successfully built and testified,such as transistors,sensors and even simple logics.How to make a best use of the self-assembled Si NWs for the construction of high-performance 3D GAA-FETs is still an open but very important question to explore.Meanwhile,the Si NWs can also serve as the ideal channel materials for large-area electronics,but a reliable integration of the vapor-liquid-solid(VLS)grown Si NWs on planar substrate surface has never been demonstrated so far.This is because the vertical VLS Si NWs need to be transferred and re-arranged on foreign substrate surfaces,where their exact position and orientations are difficult to control via scalable approaches.In order to address these challenges,our group has proposed and demonstrated a new In-plane Solid-Liquid-Solid(IPSLS)growth mode,which exploit catalyst metal droplets to absorb amorphous Si(a-Si)thin film as precursor to deposit planar Si NWs lying on the substrate surface.Importantly,the growth route of the metal droplets and thus the position of the as-produced Si NWs can be effectively guided by simple step edge lines.This thus enables a reliable integration of orderly Si NW array for the construction of various Si NW-based electronics,via a low temperature and scalable growth strategy.However,the IPSLS growth has never been explored to produce more advanced 3D nanostructures,while the planar growth of Si NWs is certainly not limited to ground surface planar substrate.Based on the IPSLS growth method,this thesis focuses on the 3D growth of stacked Si NWs along the oblique or vertical sidewall terraces,as well as their applications in high performance 3D electronic devices.In addition,a novel growth method to synthesize silicon nanowire helices(Si NHs)is demonstrated for the first time,where self-turning of the metal droplets on the corrugated sidewall surface of standing pillars helps to produce continuous 3D Si NHs via a single run growth.Importantly,the Si NHs can be released from the pillars to serve as vibrant resonators.Finally,an ultra-low temperature growth of Si NWs was demonstrated by using low-melting point metals of gallium(Ga),indium(In),and gallium-indium(Ga In)alloy,making it possible to grow crystal Si NWs directly upon organic substrates,such as polyimide(PI)or polyethylene terephthalate(PET).Specifically,there are 4 major innovations of this thesis as listed below:1)A convenient and reliable 3D growth strategy of stacked Si NW arrays has been realized along the oblique or vertical sidewall terraces,which are formed by alternating or selective etching technique and Bosch process.The prototypes of fin-TFTs and side-gated FETs based on the 3D stacked Si NW channels are also successfully demonstrated,exhibiting an impressive Ion/Ioff current ratio higher than 107 and a mobility close to 60 cm2 /Vs.The alternating etching method could be used for arbitrary inorganic substrate etching and offers a novel process for fabricating 3D structure.Three-dimensional high-density stacked crystalline silicon nanowire arrays can be used in building high-performance three-dimensional electronic devices in the future.2)A novel method to grow 3D silicon nanohelices(Si NHs)directly upon corrugated sidewalls of bamboolike cylinders has been demonstrated.The continuous moving of the metal droplets on the bamboolike cylinders surface results from the self-turning effect,caused by the shape of a-Si layer boundary and the groove of sidewalls.A dynamic model was also suggested for the two different self-turning modes of forward and backward.These Si NH arrays can be batch-manufactured with programmable diameter,layer pitch and geometry aspect-ratio.3)The 3D Si NHs can be reliably released into self-standing units to serve as elastic links,supports and vibrant,through the combination of wet and dry etching methods.The 3D Si NHs exhibit super-flexibility and could be stretched to about 240 % and fully recovered.A complex nanostructure consisting by Si NHs and PS was also constructed using probes.Importantly,the self-standing Si NHs could be affected by the external electric field and exhibit various vibration modes under different stimulated frequencies in the SEM system.4)By using Ga,In and Ga In alloy,an ultralow temperature growth of in-plane Si NWs array with precise location and designable geometry control upon plastic PI and PET thin films has been accomplished.It was demonstrated that the low temperature limit of Si NWs growth catalyzed by In and EGa In was about 160 ? and 54 ?,respectively,and the Si NWs can be effectively synthesized at 170 ? and 90 ? separately.The local crystallizing mode was proposed and indicated that it was impossible to further reduce the growth temperature,whose microscopic mechanism was also given based on the statistical thermodynamic laws.This technique could be used for large scale fabrication of flexible electronics.