Silicon Nanowire Fabrication Technology,Device Characteristics And Biosensor Applications

This thesis focuses on the above mentioned problems.Firstly,the devices with new structures which could enhance gate control abilities were explored,including S-FinFET,GAA Si NW and stacked GAA Si NW MOSFET.Furthermore,the improved device structure and electrical properties were obtained by process integration and optimization.Secondly,for future development trend More than Moore,novel Si NW sensors based on a conventional bulk FinFET flow were achieved after design and fabrication process optimizing,and were applied in the detection of cellular ion activity successfully.The main work and contributions are as follows:(1)We have discovered and solved the problem that asymmetric S-fin induced by fin etching process based on spacer image transfer(SIT)technology.A possible mechanism leading to the severely asymmetric S-fins is firstly proposed and demonstrated by reducing the heights of spacers HMs,which improves the simultaneity of etching processes and achieves the symmetric S-fins profiles.In combination with the source and drain(SD)epitaxy,a 200 ?A/?m(Lg=20 nm transistors)driving current is obtained,which reaches the performance of conventional bulk FinFETs.In addition,the S-FinFET demonstrates 25%improvement in subthreshold swing(SS)and 54%decrease in drain induced barrier lowering(DIBL)than those of control-FinFET with 20 nm Lg.With improved short channel effects(SCEs)immunity and a higher driving current,the S-FinFET provides one of promising candidates beyond bulk FinFET technology.(2)We have invastigated key technologies and integration process for the fabrication of Si NW FET.The SD parasitic resistance of insulator isolated Si NW FET was significantly reduced by using low resistance NiPt silicide at a lower temperature to form fully metallized source and drain(MSD).As a consequence,ION of transistor is increased 30 times and excellent controls of SCEs improvement over the counterpart of conventional bulk FinFETs were obtained.Meanwhile,the fully MSD process induces clear tensile stress into narrow fin-channel,resulting in the enhanced electron mobility in NMOS.A further improvement in PMOS driving current by using Schottky barrier source and drain(SBSD)technology was also explored.(3)In zero-level interlayer dielectric(ILD0)material for fabrication of GAA Si NW MOSFET has been investigated and optimizated in gate-last process.The Si NW in SD regions covered by conventional plasma-enhanced chemical vapor deposition(PECVD)of SiO2 are seriously eroded after NW releasing and surface processing,leading to failure of the device.In contrast,the processing window for the fabrication GAA Si NW channel is greatly increased,and the yield of the fabricated GAA Si NW MOSFET is increased to 79.1%using low pressure chemical vapor deposition(LPCVD)SiNx ILDO material,providing a good solution for the fabrication of GAA Si NW MOSFET.(4)A series of key module processes for the stacked GAA Si NW/NS MOSFET such as epitaxy of multi-layer GeSi/Si,selective removal of GeSi and NW release,influence of thermal budget on interfusion of multi-layer GeSi/Si,have been investigated and optimized systematically.A four-layer stacked GAA Si NS device fabricated based on mainstream bulk FinFET process are obtained by device's integration process,which could be used in 3 nm technology node and beyond.(5)The SIT technology based on a conventional bulk FinFET process was first time,applied in the fabrication of Si NW sensor,which greatly improved the efficiency and uniformity of the Si NW sensors.In addition,the Si NW sensors have been successfully applied in detection of cellular ion activity.And it is expected to have a great value in the application of drug testing platform and disease diagnosis in the future.(6)The novel hybrid image forming technology using SIT process and conventional lithography has been proposed and carried out in fabrication of the Si NW sensor with high efficiency,low cost and small variation.The Si NW sensors have been successfully fabricated on an advanced 200 mm CMOS platform.The experimental results show that the parasitic resistance of the Si NW device is reduced by 97.2%and the uniformity of the sensors is greatly improved.