Investigation Of Single Event Effects In New FinFET Device And 3D Stacked Device

Along with the rapid development on aerospace of China,it is required that space microelectronics must be high integration,high performance and low-power consumption.The space application of VLSI based on advanced technology is an inevitable trend in the development of space microelectronics technology.Compared with planar technology devices,transistor-level 3D FinFET and package-level 3D stacked devices have small size,good performance and low power consumption,which are the key devices to continue Moore's law and realize super Moore's law.For its space application,single event effect(SEE)is a bottleneck problem.Therefore,it is urgent to study the SEE of FinFET and 3D stacked devices.The main work of this paper is based on the ground accelerator simulation experiment and the GEANT4 computer simulation.The SEE of FinFET and 3D stacked SRAM and NAND flash devices was studied.The impacts of heavy ion incidence angle,heavy ion-track distribution and device package on single event upset(SEU)were systematically analyzed.The main results are listed as follows:(1)The SEE of the 14 nm FinFET technology SRAM devices was studied by the heavy ion accelerator and the GEANT4 tool.The Weibull curve of SEU cross-section varying with LET of the device was obtained by ground accelerator experiments.It was obtained that the LET threshold is 0.1 Me V/(mg/cm²)and the saturation cross-section is 1.85×10^-9 cm²/bit.The device is susceptible to multi-bit upset(MBU).With the increase of LET,the contribution of MBU increases significantly.When LET is 40.3Me V/(mg/cm²),the contribution of MBU is more than 95%.Compared with planar transistors,the specific structure of the FinFET introduced the special SEU angle effects.When the vector direction of the incident angle is consistent with the fin direction,the SEU cross-section at 60°incidence is 1.5 times higher than that at normal incidence.When the vector direction of the incident angle is perpendicular to the fin direction,the SEU cross-section at 60°incidence is 4.9 times higher than that at normal incidence.(2)The neutron SEU sensitivity and MBU characteristic of 3D die-stacked SRAM device were studied by GEANT4 tool.It was found that the trend of neutron SEU cross-section of each layer in 3D stacked device is consistent with that of the whole 3D stacked device.The SEU cross-section at 14 Me V is about one order of magnitude higher than that in the lower energy region(1 Me V-3 Me V).In the low energy region,the difference of the SEU cross-section in 3D stack devices is more obvious than that of high energy region,and can not be affected by the critical charge.The gaps of the SEU cross-section between the three layers decrease as the neutron energy increases.The SEU was mainly affected by light secondary particles,and the sensitivity of neutron SEU was influenced by the stacking pattern.The diversity,complexity and counting of MBU patterns increase with the increase of neutron energy,and the double bit upset(DBU)is the main MBU pattern.(3)The influence of the device package on SEE induced by heavy ions was studied.The SEU cross-section of the device packaged with 500?m thickness is 22.7%larger than that of the decapped device under the 100 Me V/u ²⁰⁹Bi ion irradiation.The increase of LET on the surface of the sensitive volume is the main factor that leads to the increase of the SEU cross-section of the packaged device.The contribution of secondary particles to the SEU cross-section of the device packaged with 500?m thickness is 27times higher than that of the de-capped device.Above all,this paper studied the SEU characteristics of 3D FinFET and stacked devices systematically,and the results will provide basic experimental data and theoretical basis for the design and development of irradiation harden IC based on 3D devices.