Flow Control And Optimization On Interconnection Networks In Embedded Systems

With rapid development of applications on computer and wireless mobile network, it requires more advanced equipments. In order to improve the overall performance of system, people usually use faster central processing unit (CPU). However, the parallel embedded system is more promising due to power consumption and labor force. Hence, capability of single computing unit and interconnection become the bottleneck in high performance scalable parallel computing. Since the lack of scalability and extendibility as well as the development of packet switching, serial interconnection becomes a better solution when compared with parallel bus.Flow control becomes a common choice to improve performance and robustness of system. The aim of flow control is to avoid system task being blocked by others. The arbitration algorithm is also adapted to forward packages in bus based interconnection, which insure tasks with higher priority is served in the first place. The packages enter switching networks from multiple entry point which makes centered arbitration scheme is not suitable for this scenario.The traditional flow control algorithms have bad performance in high speed transmission when transmitter is far away from receiver. There are several possible ways to improve performance of flow control: design a good topology and adopt flow control at both link layer and logic layer in order to improve system performance. This dissertation studies SRIO interconnection topology, linker layer flow control and system level flow control based on Serial RapidIO (SRIO) powered system. Details will be given in the following parts:In the first part, we introduce the concept of interconnection network and importance of flow control in interconnection network as well as the necessity of serial interconnection.In the second part, we systematically study the flow control in interconnection based on open systems interconnection (OSI) and Internet model. We also compare the interconnection and SRIO models and give some key parameters which would affect the performance of interconnection.We propose a SRIO interconnection model based on the practical problem in the third part. The robustness of link layer flow control is also studied. Then, we propose two new schemes which works well with low quality LVDS traced SRIO hardware and in low SNR environment. Simulation result shows these adaptive schemes can significantly improve system throughput and latency in severe environment.We design and implement SRIO module based on AMC standard in the fourth part. It could achieve same performance as we got from simulation results.Last but not least, we propose a new method in which receiver would send available memory information to transmitter. It could also reduce the number of retransmission. This new method could deal with the problem that the receiver does not have sufficient memory and the whole network is congested. Simulation result shows this new idea can save memory at the receiver as well as reduce traffic jam and improve the usage of bus.This dissertation concludes the research on high speed SRIO in interconnect network and propose possible directions of future work.