Research On K-band 8-channel Integrated CMOS Transmitter Front-end Chip

With the radio and semiconductor technologies developing rapidly,radar has been gradually applied to the civilian fields such as ship navigation and car anti-collision.Radar has many types.As the recent popular technique of radar,phased array radar is more flexible and reliable than traditional mechanical scanning radar,and can adjust quickly to environmental changes.While the K-band belongs to microwave near millimeter-wave,it has relatively higher resolution and smaller size,and can work in extremely bad weather circumstance.Therefore,K-band phased array radar has a considerable research value in civilian area.However,the key components of domestic millimeter-wave radar are mainly composed of discrete devices or relatively expensive Ga As chips,so it is not suitable for mass production environment.Aiming to settle the questions displayed above,this paper designs and implements an eight-channel integrated transmitter front-end chip in K-band phased array system by using the silicon-based CMOS process with stable performance and low cost.By integrating multiple channels and function circuits into one chip,it can reduce the system size in large scale,save the total payout and improve the property.Firstly,this thesis briefly states the background and significance of the topic,and analyzes the current research situation and development trends of domestic and foreign K-band phased array system based on CMOS technology.Then,the structure framework of the whole chip is planned to determine the connection sequence and initial performance indicators of the key component modules.The whole chip includes eight channel units,power distribution network,temperature compensation circuit and digital SPI module.Each channel unit is composed of phase shifter,pre-amplifier,attenuator,power amplifier.The power distribution network divides one signal into eight signals equally and sends them to eight channels.In each channel,the signal is input through phase shifter first,and initially amplifed by pre-amplifier,then adjusted through attenuator,and finally output by power amplifier.The temperature compensation module provides the DC bias changing with temperature for the amplifiers in each channel.The digital SPI module provides digital control codes for phase shifter and attenuator,and the phase and amplitude of each channel can be changed independently.Next,the article concentrates on the theoretical study and simulation analysis of three key modules:phase shifter,power amplifier and temperature compensation module,and then designs and simulates all the circuits except the digital SPI module.The phase shifter uses passive vector synthesis structure:first generate two orthogonal signals through quadrature coupler,then send to phase-invertible variable attenuator respectively,and finally use power synthesizer to combine the two signals together.The power amplifier utilize the differential common-source structure with cross-neutralizing capacitors.Here,the neutralizing capacitor is realized by the MOS capacitor,which has the same dimensions of the main transistor.The temperature compensation is used to reduce the drastic gain fluctuation with temperature.Through the superposition of two kinds of current,one is independent of temperature and the other is proportional-to-absolute-temperature,two DC bias voltages changing with temperature differently are generated.Then the comparator and selector help to complete the selection of two bias voltages for different temperature segments.The resulting bias curve shows a low temperature slope in the low temperature range and a high temperature slope in the high temperature range,which can approximately fit the ideal temperature bias curve of amplifier.Therefore,it is helpful to reduce the gain variation caused by temperature change and achieve the compensation effect.Finally,based on the circuit simulation and layout design of each portion and as well as the overall structure diagram,the eight-channel integrated transmitter front-end chip is designed and fabricated in TSMC 90nm CMOS technology.The total chip occupies2.55×5.6mm~2.The measured results of the chip present that,the total power consumption at room temperature is about 0.33W,and the power gain for the whole chip is 11.3dB at24GHz.From the range of 23.5 to 24.5GHz,the gain flatness is±0.45dB,and the output1dB compression point of each channel in the worst case is above 6.2dBm.The chip can achieve 6-bit phase shift and 16dB amplitude attenuation in each channel.For 1GHz bandwidth,the phase errors are less than 1.6°and the amplitude errors are less than0.353dB.The maximum amplitude and phase difference for the eight channels are 0.28dB and 3.5°within 1GHz bandwidth repectively.From-45℃to 125℃,the chip gain varies±2.6dB.It can be seen that the chip in this paper presents a good overall performance and can be applied in a wide range of temperature environment.