Study And Design Of Key Circuits Of Millimeter-Wave Phased Array Transmitter Channel In CMOS

Fabricated in 40-nm CMOS,this thesis presents two kinds of Ka-band differential power amplifiers(PA)for phased arrays.Based on common-source structure and Cascode structure,each of the two power amplifiers consists of driver stage and power stage.This thesis focuses on the key technologies in millimeter-wave band of the analysis and design of CMOS transistor,the transformer based matching networks and the implementation of Ka-band power amplifiers.The key technical points of PA designing are introduced.Considering the influence of transistor gate resistance,this thesis gives the optimization of structure and layout of the MOSFET.Besides,the nonlinearity of PA and the theory of impedance matching are discussed.This thesis respectively expounds the procedure of PAs designing,including confirming targets and choosing circuit topology.There exists the challenges of large substrate loss and inaccurate RF modeling in CMOS PA designing.The dielectric model is established and the electromagnetic simulation is carried out for all metal wiring and vias of the whole chip.The neutralizing capacitors is adopted for the common-source power amplifier to decrease transistor parasitic and achieve high stability.High order matching network is used to realize broadband impedance matching.In layout design,special attention is paid to the symmetry of layout and the division of AC ground of two stages.According to the simulation,the common-source PA delivers a maximum power gain of 17.8d B and wide 1d B bandwidth which covers full operating frequency.From 30.5～34GHz,the 1d B compressed power is around 12d Bm with saturated output power over 15.28d Bm and the maximum PAE of 25.3%.Parallel transistors are applied in the design of Cascode PA to reduce the parasitic resistance of gate fingers while T-model of transformer is used to accomplish impedance transformation.After completing the layout design and circuit-field co-simulation,the tape-out of the Cascode PA is carried out which occupies an area of 0.47mm~2.The co-simulation results shows that it achieves the maximum power gain of 24.2d B at 29.5GHz.Maximum saturated output power of 16.97d Bm,1d B compression power over 12d Bm and maximum power added efficiency of 26%are simulated during 27.5～31GHz.