Design And Implementation Of Charge Pump PLL Frequency Source Based On GaAs PHEMT

In the future,5G and IoT will bring fundamental changes to human work and life,but also put forward higher comprehensive requirements for communication system,including higher transmission rate,wider frequency band,greater signal transmission power and better noise performance.As the core component of 5G communication systems,the frequency source provides the excellent local oscillator（LO）signal for transceiver,and its performance plays a decisive role in the performance of the system.Ga As HEMT devices can effectively reduce the noise and improve frequency and power performance of RF circuits and systems.The charge-pump phase-locked loop（CPPLL）has the advantages of zero phase difference,low phase noise,low power consumption and easy integration.It is very important to combine Ga As technology with CPPLL in 5G and IoT environment.However,the large current performance can be achieved by using N-type transistors as current sources in compound semiconductor process,but it will also cause current mismatch and steady-state leakage,which makes it difficult to realize CPPLLs.The purpose of this dissertation is to try the design and implementation of CPPLL in compound semiconductors,which can lay the foundation for further research and development.The main content of this dissertation is to design and implement a CPPLL frequency source circuit that is used as the local oscillator in 5G communication transceivers based on Win GaAs pHEMT process.The specific research work and innovations are as follows:（1）A fully differential edge triggered frequency and phase detector（PFD）with source coupled logic（SCL）structures is proposed.In this dissertation a novel gate level conversion technique is proposed.The technique used in this circuit can solve the problem of logic errors in the hold module,realize the function of high-level sampling and low-level holding,and provide a new circuit structure for the realization of D-latches in all N-channel transistors.On this basis,the D-flip-flop（DFF）and PFD of SCL structures are realized by all N-channel transistors,which lays the foundation for the realization of GaAs pHEMT PLLs.The simulation results of this PFD show that the range of phase detector is[-355^°,355^°],the power consumption of the core circuit is 5m W,the dead time is（-5^°,5^°）,and the maximum working frequency is 500 MHz.（2）A novel charge pump（CP）with differential structure is proposed.In this dissertation,an innovative current sink control and leakage protection in the steady-state technologies are proposed.The current sink control technique can reduce the requirement of accurate matching between current sink and current source.Only the current of the current sink is greater than or equal to that of the current source,which reduces the difficulty of the design and improves the implementability of the charge pump.When the charge pump is stable,the mismatch between current sink and current source will cause charge leakage,and the charge pump will become unstable.The leakage protection in the steady-state technique can prevent the leakage behavior of the capacitor in the loop filter to the current sink module.This makes the output control voltage remain unchanged when the loop is locked,which meets demand of compound semiconductor charge pump PLLs.The simulation results of the charge pump show that the I_CP of charge pump current is 7 m A,the static power consumption of charge pump is 56 m W,the area is 530μm×743μm,the control voltage range is 1 V to 3.5 V.（3）A low noise voltage-controlled oscillator（VCO）used in PLL is realized.The out-of-band noise of a PLL is mainly determined by a VCO,so the structure selection and design of a low noise VCO are particularly important.The cross-coupled VCO not only has the lower phase noise,but also has the advantages of simple structure and easy oscillation starting.The measurement results show that when the control voltage changes from 0 V to 3 V,the tuning range is 0.72 GHz,and the output oscillation frequency is 3.23 to 3.95 GHz.When the control voltage is 2 V,the phase noises of the VCO are-98.4 d Bc/Hz at 100 KHz,-112.78d Bc/Hz at 1 MHz and-129.52 d Bc/Hz at 10 MHz,respectively.The power consumption is81 m W,and the area is 1.016 mm×0.614 mm.The phase noise and frequency performance of a VCO can be restricted by each other,so it is difficult to achieve good performance at the same time.In this dissertation,a novel anti-phase coupled transmission lines structure is proposed.This structure replaces DC-blocking capacitors and load inductors,and improves the frequency characteristics and integration of the VCO.The mutual inductance effect produced by anti-phase coupling can not only reduce the inductance and further increase the oscillation frequency,but also improve the quality factor of the resonant circuit and reduce the phase noise.The test results show that the control voltage varies from-1.5 V to-0.5 V,the tuning range is 5.5 GHz,and the oscillation frequency is 28.612 to 34.13 GHz.When the center frequency is 31.371 GHz,the phase noise is-113 d Bc/Hz,FOM_TP is-193.4 d Bc/Hz,the power consumption is 45 m W,and the area is 0.45×0.57 mm².（4）A wideband analog divider is implemented.In a PLL,the frequency change of a VCO is often caused by the load-pull effect.If the bandwidth of a divider is not enough,the frequency of the VCO and divider cannot match the criterion,and the PLL will lose lock.In this dissertation,a trans-impedance amplifier with resistive shunt-shunt feedback and shunt-peaked inductor as the active load of the analog divider can increase the loop bandwidth and frequency loop gain,thereby expanding the bandwidth.In this dissertation,based on Win 1μm Ga As HBT process to realize the analog divider,the total chip area is 0.83 mm×0.75 mm.The measurement results show that the output phase noise of the divider is less than-110d Bc/Hz at 100 KHz offset and-127.6 d Bc/Hz at 1 MHz offset,the operating frequency range is 10 GHz～26 GHz,and the bandwidth is 16 GHz,the power supply voltage is-6 V,and the total power consumption is 166.44 mw.On this basis,the SCL structure based on N-channel transistor is developed,which provides a new circuit structure for the implementation of static frequency divider.The test results show that the frequency divider can realize the frequency division function in the frequency range of 0 GHz～4.8 GHz,and the area of the chip without pads is 0.624 mm×0.923 mm.（5）The phase-locked loop of the charge pump is designed and studied with the GaAs pHEMT process.Based on the simulation results,the layout design of the phase-locked loop is completed.Finally,based on Win PL 15-12 GaAs pHEMT process,the charge pump phase-locked loop was taped-out.Measurement results show that the output signal frequency of GaAs pHEMT CPPLL is from 3.584 to 4.021 GHz,and the bandwidth is about 0.44 GHz.Within its working frequency range,the lowest phase noises at the frequency offset of 100k Hz,1 MHz and 10 MHz are-90.03,-117.82 and-137.89 d Bc/Hz,and the maximum output power is 4.34 d Bm.The chip area is 2701×3381μm²,and the power consumption is 181 mw.The GaAs pHEMT CPPLL designed in this dissertation has good performances and can be used as local oscillator signal sources in 5G wireless transceivers.