Design And Key Technologies Of Novel MOSFET With Majority Carrier Conductance Modulation

As the core device for processing electric energy,power semiconductor devices are widely used in the Internet of things and information computing centers,new energy vehicle charging piles,locomotive traction,photovoltaic new energy,high-voltage power transmission and other fields.High performance power semiconductor devices can greatly reduce the energy loss in the generation,transmission and use of electric energy.Researchers have proposed a variety of methods to continuously improve the performance of power semiconductor devices.For fixed voltage applications,continuously reducing the specific on resistance（Ron,sp）is the focus of optimal design.However,the enhanced depletion principle is most used to design new devices in the medium and high voltage applications at the present.The Ron,sp is reduced by increasing the doping concentration with various techniques.In this dissertation,the majority carriers are introduced to realize the conductance modulation of the drift region,and the current of the proposed structures mainly depends on the introduced carriers rather than the doping.This method can greatly reduce the Ron,sp and break through the design limit of conventional devices.Firstly,the significance of the development direction of power devices and common terminal technologies are analyzed.A new type of accumulation sustain voltage layer is proposed for the drift region.The relationship between the Breakdown Voltage（B V）and Ron,sp is better than "silicon limit" and“SuperJunction（SJ）limit".Then the vertical accumulation devices are proposed based on the accumulation sustain voltage layer,including Accumulation-mode Vertical MOSFET with Gate electrode（GA VDMOS）,Accumulation-mode Vertical MOSFET with Extra electrode（EA VDMOS）,Accumulation Lateral Double-diffused MOSFET with N Buffer Layer（Ac-NBL LDMOS）,and accumulation Lateral Double-diffused MOSFET with Variable Resistivity of drift region（VR LDMOS）.In addition,an Accumulation SuperJunction Vertical MOSFET（Ac-SJ VDMOS）is proposed by combining the accumulation sustain voltage layer and SJ theory.According to Poisson equation,the electric field distributions and current distributions of GA VDMOS and Ac-NBL LDMOS are solved.The relationships between the BV and Ron,sp of GA VDMOS and Ac-NBL LDMOS are obtained,respectively.The new accumulation LDMOS compatible with BCD（BipolarCMOS-DMOS）process are completed:Planar Accumulation Lateral Double-diffused MOSFET（PA LDMOS）,Folded Accumulation Lateral Double-diffused MOSFET（FA LDMOS）,and Folded Accumulation Lateral Double-diffused MOSFET with Split gate（FS LDMOS）.Finally,the experiment is realized on the same wafer through the custom process flow,and the results are tested and analyzed.The main innovations of this dissertation are as follows:（1）The conventional sustain voltage layer is analyzed,and it is found that the relationship between the BV and Ron,sp represented by the "silicon limit" is not the lowest Ron,sp that the silicon material can achieve with the single doping condition.A new "siliocn limit" of single doping is obtained based on the analysis of the electric field of punchthrough drift region.（2）An adaptive drift region resistivity technique is proposed.The conductivity in the drift region is adjusted by the gate voltage.When the device is turned off,the drift region has a high resistivity to sustain the B V,and when the device is turned on,the drift region has a low resistivity to transmit current.The resistivity of the drift region changes with the gate voltage,which can greatly reduce the Ron,sp while maintaining a high BV.An accumulation sustain voltage layer is proposed.The accumulation sustain layer greatly optimizes the relationship between the BV and Ron,sp(Ron,sp∝B V^1.108),breaking through the "silicon limit"(Ron,sp∝BV^2.5)and "SJ limit"(Ron,sp∝BV^1.32).（3）The GA VDMOS and EA VDMOS are proposed based on the accumulation sustain voltage layer.The breakdown characteristics can mainly be optimized by reducing the doping concentration of the drift region.The excellent conduction characteristics can be mainly achieved by reducing the thickness of the accumulation oxide layer or increasing the voltage of the accumulation electrode.The analytical modes of the internal electric field distributions and current distributions are solved with simulation.The advantages of the split design of the breakdown characteristics and conduction characteristics have been verified.When the length of the drift region is increased from 10μm to 30μm,the BV of the GA VDMOS is increased from 253V of the conventional VDMOS to 613 V.By introducing accumulated electrons to the SJ device,an Ac-SJ VDMOS is proposed,which further reduces the Ron,sp.（4）The Ac-NBL LDMOS and VR LDMOS are proposed based on the accumulation sustain voltage layer.When the accumulation sustain voltage layer is directly applied to the lateral devices,the two-dimensional effect of the PN junction formation between the drain and the substrate produces electric field concentration,resulting in a lower BV.The Ac-NBL LDMOS uses an N-type buffer layer to improve the electric field distribution in the substrate and eliminate the two-dimensional effect of the PN junction.In order to enhance the accumulation electron density,the VR LDMOS adopts the Schottky junction to replace the PN junction in the accumulation sustain voltage layer,which further reduces the Ron,sp.The analytical model of the electric field inside the Ac-NBL LDMOS is solved by Poisson equation,and the modulation effect of the N-type buffer layer on the electric field is verified.When the BV is 228V,the Ron,sp of the conventional LDMOS is 29.8 m2·cm2.The Ron,sp of Ac-NBL LDMOS and VR LDMOS are 2.4 mg·cm2 and 1.5 mΩ·cm2,respectively.（5）The tape-out experiments of PA LDMOS,FA LDMOS and FS LDMOS have been completed by BCD process.The extended gate metal enhances the depletion of the drift region,thereby increasing the doping concentration while maintaining the BV.More importantly,the accumulation the path of electrons are introduced into the drift region,which together greatly reduces the Ron,sp.The BV of PA LDMOS and FA LDMOS is about 36V,and the Ron,sp is 64.3%and 74%lower than that of conventional LDMOS,respectively.In order to disperse the electric field at the edge of the extended gate,an FS LDMOS is proposed.When the drift region length is 3μm,the BV is 66%higher than that of the FA LDMOS,which broadens the voltage application range of the extended gate devices.In this dissertation,the idea of using majority carriers to modulate electrical conductivity is proposed,and accumulation sustain voltage layer is proposed.Then 9 new accumulation mode power devices are designed.The relationship between BV and Ron,sp has been greatly improved.The mathematical analytical models are established for the vertical accumulation device and lateral accumulation device,respectively.The design parameters of the accumulation devices are quantitatively analyzed.The new accumulation devices that can be integrated by the customized BCD process technology are studied.The key manufacturing process are explored,and the results are tested and analyzed.