Design Of Novel Power Devices With Si/SiC Heterojunction

As a core part of power electronics technology,power semiconductor devices have promoted the rapid development of power electronics technology.The two key parameters for measuring the performance of power semiconductor devices are the breakdown voltage and specific on-resistance.Silicon-based power MOS devices are currently mainstream commercial power semiconductor devices.For silicon-based power MOS devices,researchers have been optimizing the performance of the device from three aspects of structure,process and material.Although researchers are still working hard to develop new silicon-based power MOS devices,the performance of the device exists the“silicon limit”due to the limitation of the critical breakdown field of the silicon material.In addition,silicon material is not suitable for working in special environments such as high temperature,high voltage,and high radiation.As the third generation semiconductor materials,SiC attracts much attention due to its wide band gap,high critical breakdown electric field,high thermal conductivity and strong anti-radiation.However,the process of the SiC MOS devices is yet instability,and can't fully adopt the silicon device process.In order to solve these problems of power semiconductor devices,based on Si/SiC heterojunctions with interface properties studied by previous researchers,three structures are proposed in this paper:Si/SiC heterojunction VDMOS,Si/SiC heterojunction UMOSFET,and Si/SiC heterojunction LDMOS.The main innovations of this paper are as follows:A novel Si/SiC heterojunction VDMOS structure is proposed and its performance is simulated.Breakdown point transfer technology is firstly proposed in this paper.Compared with Si VDMOS,it can undertake higher voltage and better heat dissipation performance.When the drift region length is 15μm,The optimized breakdown voltage of the new structure is increased from 226V to 578V compared with the conventional Si VDMOS,and the breakdown voltage is increased by 155.7%.For the forward conduction,the specific on-resistance of the new structure is 17.4mΩ·cm~2 with the breakdown voltage of 578V,which is lower than that of 41.01mΩ·cm~2 with the breakdown voltage of 226V in Si VDMOS,and the specific on-resistance is reduced by 57.5%.The relationship between the breakdown voltage and the specific on-resistance of the structure breaks through the silicon limit.A novel Si/SiC heterojunction UMOSFET structure is proposed and its performance is simulated.The simulated results have been shown that when the drift region length is 5μm,the optimized breakdown voltage of the new structure is increased from 107V to 358V compared with the conventional Si UMOSFET,and the breakdown voltage is increased by235%.For the forward conduction,the optimized new structure has an ultra-low specific on-resistance of 0.51mΩ·cm~2 with the breakdown voltage of 358V,the specific on-resistance of Si UMOSFET is 1.12 mΩ·cm~2 with the breakdown voltage of 107V,and the specific on-resistance is decreased by 54.4%.Due to the advantages of SiC materials in the new structure,the performance of the device breaks through the silicon limit and the super-junction limit.A novel Si/SiC heterojunction LDMOS structure is proposed and its performance is simulated.The simulated results have been shown when the drift region length is 30μm,the optimized breakdown voltage of the new structure is increased from 261V to 448V compared with the conventional Si LDMOS,and the breakdown voltage is increased by71.6%.For the forward conduction,the merit value of the Si/SiC heterojunction LDMOS is increased from 0.91MW/cm~2 to 2.35MW/cm~2 with the conventional Si LDMOS,and the merit value is increased by 158%.