Research On Key Technologies Of High-performance Nanoscale CMOS Phase-locked Loops

Phase-locked loops with high-purity spectral are critical in today’s communication systems.With the widespread popularity of various terminal products,the phase-locked loops also need to have low power consumption and cost.Nowadays society,whether it is high-speed wired communication or radio frequency wireless communication,higher requirements are placed on the phase-locked loops.Massive data transmission makes the phase-locked loops have wider range frequencies,faster locking time and high frequency resolution,etc.In communication systems,such as radar,locking time of the phase-locked loop is beneficial to information security and anti-jamming capabilities.In early designs,the phase-locked loop consisted of a single frequency band,and the locking time was related to the loop bandwidth.However,in view of the stringent jitter requirements of current products,VCO usually contains multiple frequency bands,so a lower frequency gain(KVCO)can be obtained with a wider output range.The problem is that the target frequency band needs to be confirmed first in the locking process.Therefore,the locking time is increased greatly.In terms of noise optimization of the charge pump phase-locked loop(CPPLL),CP noise tends to dominate the in-band phase noise of the phase-locked loop,while the out-band noise is dominated by the VCO.In conventional CPPLLs,CP noise can be reduced by shortening the dead-zone time of the phase detector and increasing the CP current.Among them,the dead-zone time is related to the process,and it is difficult to improve in the design.In terms of CP current,the in-band noise can be reduced by 3 dB theoretically with doubling CP current,but the optimization has a certain limit.In the products,most parameters of the phase-locked loops have been set,such as the reference frequency and the output frequency,which greatly reduces the flexibility of the design.In order to place the bandwidth near the noise intersection,there is a tradeoff between CP current and impedance of the loop filter.In order to solve the above problems,the research contents of this dissertation are as follows:First of all,this dissertation studies and details the mainstream phase-locked loops,systematically,such as CPPLL,sub-sampling phase-locked loop(SSPLL),injection-locked phase-locked loop(ILPLL),etc.In addition,research is carried out on the cascaded phaselocked loops,which is widely used in high-frequency systems.By analyzing the s-domain model and the noise transfer function,it provides a theoretical basis for the system-level optimization of phase-locked loops.Then,this dissertation analyzes and designs the key modules in CPPLL,and provides a phase noise optimization technique for wideband voltage-controlled oscillator(VCO).The key modules of CPPLL including frequency and phase detector(PFD),CP,VCO,frequency divider(Divider)and so on.Through theoretical analysis on principle,design,noise,etc.,it is beneficial to optimize the noise of each module in the design.And it provides the realization and theoretical basis for the subsequent chapters.In the section of VCO,by analyzing the relationship of the amplitude,current and capacitance,an adaptive compensation technique is proposed,which reuses the output code of the Automatic Frequency Calibration(AFC)circuit.The technology is verified at a 4.1-5.2-GHz VCO,the phase noise is-124 dBc/Hz@1MHz and the FOM is-190.25 dBc/Hz at 5-GHz output.Meanwhile,the optimization of phase noise at 4.1-GHz output is the best,which is 2.05dB.Based on 65-nm CMOS process,this dissertation designs a power-efficient time-to-voltage converter(TVC)-based fast AFC technology.The technology is based on a divide-by-3 circuit that can realize a single-cycle pulse signal,and the preset operation is added in the divide-by-3 circuit.Then,based on the preset operation,the sampling of the reference and feedback frequency is realized,which greatly reduces the circuit complexity and the noise sources.And it alleviates the problem of design accuracy.At the same time,the reference frequency is reused,and it avoids the application of additional clocks.Besides,in order to solve the problem of voltage margin in TVC-based AFC,a binary-like frequency search algorithm is proposed.Verification shows that the single calibration cycle of the proposed AFC is three reference cycles,and the total calibration time is less than 375 ns when the binary digital controlled capacitor array(DCCA)is 4 bits and the reference frequency is 40 MHz.Compared with the single-band locking times,which is usually several μs or even tens of μs,the calibration time of the proposed AFC is almost negligible.Based on 65-nm CMOS process,this dissertation proposes a dual-path phase-locked loop(DPPLL)with fast CP mismatch calibration.In order to reduce the CP noise in the traditional CPPLL and solve the parameter flexibility,this dissertation adopts a DPPLL with flexible parameters and a small area.Moreover,the problem of spurs in DPPLL is improved.The improvement is a fast CP mismatch calibration.By briefly establishing a CP calibration loop in the phase-locked loop,the calibration cycle of CP can be shortened to a reference period.It is calibrated by successive approximation,and the calibration method is binary.In addition,the reset voltage of integral path for calibration is provided by the locked voltage,that is,the real-time CP mismatch is calibrated at the target frequency,which greatly improves the calibrated accuracy and speed.The phase noise is-102 dBc/Hz at 100-KHz frequency offset(frequency division ratio is 128).A-64.91-dBc reference spur is achieved before calibration,and a-74.02 dBc is acquired after calibration.Thus,the reference spur is improved by 9.11 dB.The integrated jitter after optimization(integration bandwidth 10 K-20 MHz)is 335.4 fs at 5.5-GHz output.