Research And Design Of Low-power SAR ADC

Analog-to-Digital Converters(ADCs)play a crucial role in electronic systems,bridging the physical world with digital circuits.Successive Approximation Register(SAR)ADCs excel in low-power applications due to simplicity and low power.With advancements in technology,traditional analog circuit designs face challenges,while SAR ADCs,owing to digital structures,exhibit outstanding performance in advanced technology.The demand for low power in mobile devices makes research on SAR ADCs particularly urgent,as they directly impact battery life and user experience.As industries demand higher ADC accuracy,research into high-precision ADCs becomes crucial.Traditional methods like oversampling have limitations,especially for rapid response needs.SAR ADC and Pipeline SAR ADC stand out for their low power consumption,high accuracy,and suitability for multi-channel.This dissertation aims to explore design strategies for these high-precision ADCs to meet the needs of industries such as industrial control,instrumentation,and medical devices.This dissertation focuses on the circuit design and architecture of SAR ADC and Pipeline SAR ADC,discussing key issues such as low-power comparator and amplifier,sampling noise,and capacitor mismatch calibration.After introducing the research background and significance,it provides fundamental knowledge of SAR ADC and Pipeline SAR ADC,with operation,performance metrics,and other non-ideal factors.Key technologies such as comparator optimization,amplifier design,and capacitor mismatch calibration are detailed.Based on traditional techniques,the dissertation proposes methods to enhance the performance and efficiency of SAR ADC and Pipeline SAR ADC:(1)VCO comparator with gain boost and metastability reduction: Utilizing current reuse techniques increases the voltage-to-time gain of the VCO without extra power consumption,improving comparison speed and noise performance.Furthermore,by adjusting the dead-zone size internally through feedback within the phase detector,the probability of encountering metastability is successfully reduced.(2)Dynamic bias comparator integrated with VCDL: Integrating a VCDL as the first stage before the dynamic bias comparator converts voltage to a time-domain signal,boosting the dynamic bias amplifier’s speed while maintaining its characteristics.This enhances noise performance and reduces power consumption,achieving a better balance between speed,noise,and power.(3)Low-noise comparator based on floating inverter amplifier with adaptive delay line: This comparator improves traditional designs based on floating inverter amplifier.It introduces an adaptive delay line to enhance preamplifier gain under small input signals,reducing overall noise by minimizing latch stage noise.(4)14-bit,50 MS/s SAR ADC with switchable delay control and pre-reset mechanism: Building upon the comparator mentioned in(3),this design introduces switchable delay control for the first nine cycles,sacrificing noise performance for speed.It then switches to low-noise mode for the remaining quantization cycles,reducing noise through adaptive delay.Additionally,a pre-reset mechanism minimizes time overhead by resetting the comparator in advance.(5)Improvement of linearity and noise reduction in switched-capacitor amplification:This design combines Correlated Level Shifting(CLS)and noise bandwidth switching to increase equivalent open-loop gain and reduce output noise.Compared to traditional approaches,it elevates SFDR from 51 d B to 88 d B,while reducing output noise from583.3 V to 450.8 V.(6)Sampling thermal noise cancel with signal bandwidth enhancement and linearity improvement: This technique employs a differential circuit compensation path to address amplifier output saturation issues under high-frequency input signals,thereby enhancing system bandwidth and linearity.Simulation results demonstrate an increase in SFDR from83.1 d B to 117.7 d B and a reduction in total equivalent input noise(including sampling thermal noise and residue amplifier noise)from 113 V to 39.8 V when the input frequency is approximately 5 MHz.(7)Design of an 18-bit 4 MS/s Pipeline SAR ADC with signal independent capacitor mismatch calibration: This design implements background signal independent calibration for capacitor mismatch by employing shuffler,swap,and bypass,along with perturbation injection,within a Split ADC structure.Additionally,double weights mechanism is used to calibrate reference voltage deviation.