Study And Design Of Silicon Based Clock And Amplifier Key Circuits For Communication And Sensing Applications

Intelligent communication and sensing is one of the key techniques in 5G/6G communication,which can effectively support the applications of intelligent emerging services such as virtual reality,holograms,pilotless automobile,robot automation and factory automation.To overcome the key bottlenecks of above applications,it is urgent to develop the ultra-high data rate communication and high precision sensing techniques with millimeter wave（mm Wave）spectrum and superconducting nanowire single photons（SNSPD）.Clearly,the development and realization of the integrated circuits is the foundation and essential part of communication and sensing applications,which is a great significance for enhancing China’s competitiveness in the area of mobile communication and intelligent sensing,as well as constructing future ubiquitous network system.With the advantages of low cost and high integration of silicon process,targeting at the applications of single photon detection,mm Wave radar and communication,this dissertation focuses on the design of amplifiers and clock circuits.The main research content and contributions are summarized as follows:1)For cryogenic SNSPD applications,this work presents the design and implementation of SNSPD readout circuits.Considering the lack of cryogenic device model and large performance variation of the devices over temperature,a temperature-insensitive wideband cryogenic amplifier was proposed based on Bi CMOS silicon process.To improve the gain stability over large temperature range and the noise performance,a folded diode-connected transistor load is realized.The chip was tested both at room and cryogenic temperature.The test results agree well with theoretical derivations and simulation results,which proves that the amplifier gain cell has a stable gain performance over a wide temperature range,solving the lack of the accurate cryogenic device model issues.Test results show that the chip achieves a gain of 26 d B at 4.2 K,with a bandwidth greater than 1 GHz,while consuming a power consumption of only 1.8 m W.By connecting the SNSPD and the readout chip,the single photon signal is successfully detected.In addition,a4-channel readout chip is implemented for the future SNSPD array detection applications.2)For mm Wave communication and radar sensing applications,based on a 40 nm CMOS process,the design and implementation of 77 GHz and 90 GHz power amplifiers（PA）are undertaken.As the supply voltage of nano-CMOS devices is very low,the output power of PA is severely limited.To solve these issues,transformer based power combining technique is employed.To improve the amplifier bandwidth,area efficiency and to reduce the insertion loss of the matching network,a hybrid impedance matching scheme is adopted by combining the transmission line and transformer.In order to further reduce the passive insertion loss and to improve the circuit stability,a theoretical analysis of transformer optimization is carried out first.Then an analysis of the common-mode stability based on the transistor model is undertaken from the impedance perspective.With an on-chip probe test,it is found that the output power of the 77 GHz PA is about 19 d Bm with a gain of more than 20 d B.Moreover,the PA small signal bandwidth is more than 13 GHz and the maximum power added efficiency(PAE_max)is 20%.With a similar test scheme,the 90 GHz PA shows an output power of 19 d Bm with a gain of more than 22 d B.Moreover,the PA small signal bandwidth is more than 19 GHz,and its PAE_max is about 12%.Compared with the literature results,the 90 GHz power amplifier has the highest power gain over other CMOS PAs operating under similar frequency range.3)For broadband high-speed mm Wave communication applications,based on a 65nm CMOS process,a 48 GHz phase locked loop（PLL）is presented for 60 GHz mm Wave communication.First of all,the system structure and link budget are given for 802.11ad communication standards.Secondly,for the sliding intermediate frequency（sliding-IF）transceiver architecture,a local clock generation scheme is proposed based on PLL and local frequency divider.Specifically,with an implicit capacitive-bridged shunt peaking network,a second order harmonic filtering technique is realized in the voltage control oscillator（VCO）to broaden the bandpass response,thereby avoiding the complex common-mode resonant tank calibration and improving the phase noise performance.The current mode logic（CML）static frequency divider topology is adopted to realize the prescaler and to generate the quadrature clock.With a dedicated biasing circuit,the reliability of static frequency divider is enhanced.In addition,the scheme of amplitude stabilization and quadrature clock phase calibration was proposed,thereby realizing orthogonal clock generation and improving the image suppression performance of the RF transceiver.On the other hand,the digital serial peripheral interface（SPI）and calibration module are used to realize circuit control and frequency calibration,respecetively.With test,the PLL performance can be summarized as follows:phase noise lower than-97 d Bc/Hz at 1 MHz offset;integrated phase noise less than-29 d Bc;the jitter less than 155 fs,spur less than-60 d Bc.Moreover,the PLL tuning range fully covers the 60 GHz frequency band.Compared with the literature results,the PLL achieves the best integrated phase noise,jitter and spur performance.Finally,the 48 GHz PLL is integrated with the transmitter and receiver,and the first 60 GHz CMOS fully integrated wireless transceiver chip in China is successfully realized.Test results show that the transceiver chip can support 16QAM modulation scheme with a data rate of 14 Gbps.By combining the mm Wave frondend and baseband,a real time wireless high-definition（HD）video transmission demo is also undertaken.