Research On Model And Novel Structure Of Low Loss Power MOSFET

Power semiconductor devices,which are indispensable basic and core components in realizing miniaturization,intensification and intellectualization of power electronics equipment,can effectively reduce system power loss,increase system efficiency,increase system equipment reliability,and reduce system cost in applications.Ever since the invention and widely utilization of the trench MOSFET structure,researchers have conducted innovative studies in four aspects,which are the optimization of the trench MOSFET structure,super junction MOSFET,field plate MOSFET and split gate MOSFET,to achieve power MOS devices with lower power loss.The proposal of characteristic process power products has achieved an innovative approach more than moles,and“Power Core”based on power devices has become the best breakthrough point of“China Core”.Continuing to tap the potential of power MOS devices,studying the structure and technology of lower on-resistance,smaller chip area and faster switching speed,maximizing the advantages of power MOS devices in driving,switching and other aspects,are unremitting pursuits of researchers.By taking low loss power MOS devices as the research object,this dissertation studies theoretical models,structures,designs and process realization of low power loss MOS devices.An analytical breakdown voltage model of trench power MOS devices and a Si-Al double diffusion model of submicron devices are proposed.A novel submicron trench power MOS device,three novel split gate trench power MOS devices and a novel vertical bidirectional power MOS device,are proposed.Main innovation points are as follows:（1）An analytical breakdown voltage model of trench power MOS devices,a Si-Al double diffusion model of submicron devices and a novel submicron trench power MOS device structure are proposed.By establishing a two dimensional analytical breakdown voltage model of the trench power MOS device,a two dimensional electric field distribution profile of the drift region is obtained,the most optimal breakdown criterion is concluded,the influence of structure and process parameters upon the breakdown voltage（BV）and specific on-resistance(R_on,sp)of the device is acquired,and the optimal design of the trench power MOS device is realized.On account of this model,the novel submicron trench power MOS device structure,whose cell pitch reaches 0.5μm,is proposed and designed.Meanwhile,in order to develop this device,the Si-Al double diffusion model is proposed.By conducting qualitative analysis in the diffusion region and semi-quantitative analysis based on the source diffusion with constant impurity and non-stationary diffusion,the relative diffusion coefficient and concerntration distribution profile of Al under failure state,critical state and reliable state are obtained.On account of this model,the influence of the metal dielectric layer on the Al-Si double diffusion is discussed.A novel Al-Si double diffusion process is proposed and experimentally verified.Experiment results show that the submicron trench device has a BV of 26.2 V and a R_on,sp of 3.58 mΩ·mm².Compared with current low voltage trench power MOS devices in batch production,the figure of merit value(BV²/R_on,sp)of the new device is improved by 35.5%and the power loss is further reduced.（2）Novel device structures of low power loss split gate trench power MOS（SGMOS）are proposed.First of all,the conventional low voltage SGMOS is optimized and analyzed,and its terminal breakdown voltage degradation mechanism is studied.On account of this,a novel SGMOS with inverted L-shaped source region structure is proposed.A source implantation process,which is characterized by four-quadrant tilt implantation,is designed to realize the fabrication of it.The fabricated device has a measured BV of 38.5V and a figure of merit value(R_on?Q_G)of 157.5 mΩ·n C.Compared with other low voltage SGMOS with the same voltage rating,a performance improvement of 18.2%is achieved.A novel SGMOS with narrow gate structure is proposed.The structure is realized through the narrow gate formation process which is familiar with the conventional side wall formation process.The fabricated device has a BV of 25 V and a figure of merit value(R_on?Q_G)of 34.1 mΩ·n C.Compared with other low voltage SGMOS with the same voltage rating,a performance improvement of 11.7%is achieved.Besides,a novel SGMOS with stacked insulator structure is studied and optimized.The stacked insulator structure refers to the adoption of a multilayer dielectric structure to replace the isolation oxide layer between the field plate polysilicon and the N drift region to achieve adjustable equivalent permittivity under the same equivalent thickness,optimize the electric field distribution profile of the drift region,reduce the resistance of the drift region,and reduce the power consumption of the device further.In addition,the stacked insulator structure can also reduce the process risks caused by the reduction of the SGMOS cell pitch.（3）A stacked packaging design of low power loss MOS bidirectional switches,an integrated packaging design and a new vertical bidirectional power MOS switch are proposed.By utilizing the submicron trench structure,a power MOS bidirectional switch which integrates a sampling power MOS device is designed.The stacked packaging design,which realizes a three-layer packaging of the power MOS bidirectional switch,the data acquisition chip and the control chip,is proposed to realize the chip-level integration and the system-level packaging of power switches.By utilizing the split gate trench structure,a power MOS bidirectional switch which integrates pre-charge and pre-discharge power MOS devices is designed.The integrated packaging design of power MOS bidirectional switches is proposed to improve the uniformity between the power MOS devices,and reduce the system-level cost.Besides,a vertical bidirectional power MOS switch is proposed.The switch converts the traditional bidirectional dual die design into a single die design and a dual-channel U-type current path into a single-channel vertical current path,which reduces the overall size of the power switch and realizes the reduction of the conduction impedance.The designed power MOS switch with 20 V bidirectional breakdown voltage has an extremely low R_on,sp of 1.84 mΩ·mm².