Research On Reliability Problems Of STT-MRAM

With the continuous shrinkage of CMOS process feature size,the CMOS memory is faced with severe challenges,including short-channel effect,quantum tunneling effect and parasitic effect,etc.The problems of "memory wall" and "power wall" become more prominent.The cutting-edge memories are expected to be the candidate to break through the limitations of the "two walls".The related research becomes one of the important hot spots in the research community.Spin Transfer Torque Magnetic Random Access Memory(STT-MRAM)shows the advantages of high integration,fast read/write speed,and non-volatility and is known as one of the universal memories.STT-MRAM has potential applications in industrial automation control,Internet of Things(Io T),communication,aerospace,etc.With the continuous development of the integration of STT-MRAM,the reliability problem becomes more serious,which hinders the practical application of STT-MRAM.In the thesis,the influences of the electrostatic discharge(ESD),the magnetic field interference,and the irradiation effect on STT-MRAM reliability are studied.Based on the theory of magnetization dynamics,as well as the optimal control approach of the key parameters,the simulation models of STT-MRAM memory cells and the memory arrays are established.The mechanisms of the influences of the electrostatic field,the external magnetic field,and the irradiation environments on the reliability are investigated.The technical solutions to improve the reliability of STT-MRAM are proposed.The related simulation validations are carried out.The main research contents of the thesis are as follows:1.To address the issue of the reliability degradation of STT-MRAM in the case of the electrostatic discharge(ESD),a novel ESD protection strategy for STT-MRAM is proposed.Firstly,based on the human body model(HBM),machine model(MM)and charged device model(CDM)of ESD discharging event,the simulation model for STT-MRAM electrostatic influence is established.The mechanisms of the electromagnetic influences of different ESD events on STT-MRAM memory arrays are studied.Based on the magnetic dynamic mechanism of Magnetic Tunnel Junction(MTJ)of the memory cell,the influence of ESD events on the reliability of STT-MRAM is verified.The influences of the transient magnetic field induced by ESD current under different memory densities and array structures are investigated.Based on the above research results,the ESD protection circuit of STT-MRAM is designed.The protection effect of the protection circuit under different ESD mechanisms is verified.2.To address the issue of the influence of the external magnetic field on the reliability of STT-MRAM,the STT-MRAM magnetic immunity mechanism is studied.Firstly,the influence of the external magnetic field on MTJ device is analyzed theoretically.The influence mechanism of the external magnetic field on the magnetic immunity of STT-MRAM is studied.The mapping relationships of the external magnetic field on the thermal stability factor,the magnetic field duration time and the operating temperature of MTJ device is established.Secondly,the simulation model of STT-MRAM array is established to study the influences of the electrode thickness,the insertion layer thickness,the package material thickness,the array spacing and the pinned layer thickness on the magnetic immunity of STT-MRAM.The effects of the external magnetic field and the temperature on the magnetic immunity of STT-MRAM in the standby state,active read state and active write state are also studied.Based on the Quad Flat Package(QFP)and Ball Grid Array(BGA)package technology of STT-MRAM,the magnetic shielding structure is designed to enhance the magnetic immunity of STT-MRAM.3.To address the impact of aerospace irradiation environment on STT-MRAM reliability,the STT-MRAM read/write circuits with pipeline architecture is proposed.Based on the results in the previous two sections,STT-MRAM memory array with high reliability is designed.The radiation hardening of STT-MRAM with write-termination pipeline read-write circuit is designed.Triple Modular Redundancy(TMR)radiation hardening design is carried out to fulfill the STT-MRAM peripheral circuit with high anti-irradiation performance.In addition,the radiation hardening technology of the peripheral circuit key nodes is studied.The radiation hardening STT-MRAM multi-bit pipeline structure is proposed.Based on Dual Interlocked Storage Cell(DICE),the radiation hardening shift register circuit is designed to realize the parallel read and write operations of serial data.Based on the above design,the anti-irradiation performance is upgraded and the read/write efficiency of STT-MRAM is improved.