Study Of Single-Event Multiple Upset And Transient Effect On 28 Nm SRAM-based FPGAs

With the rapid development of integrated circuits,the feature size of devices continues to shrink,and the integration level of chips continues to improve.As is known,static random-access memory（SRAM）-based field programmable gate array（FPGA）,as a typical representative of advanced integrated circuits,has become the core component of digital-circuit systems in aerospace applications.However,the space radiation environment where spacecraft are located can cause single-event effects in SRAM-based FPGAs,which seriously threaten the safety of on-orbit spacecraft.Single-event effects in SRAM-based FPGAs are mainly manifested as multiple upsets caused by heavy ions and circuit functional failures caused by single-event transient（SET）.When the feature size of devices shrinks to the nanoscale,the multiple-upset and circuit-failure modes in SRAM-based FPGAs become more complex,and their mechanisms are diverse,which are the hot and challenging topics in single-event-effect research.Therefore,it is urgent to carry out in-depth the single-event-effect experiment and mechanism research,as well as perform the radiation-hardening design on nanoscale SRAM-based FPGAs.In this study,systematic heavy-ion irradiation experiments on a 28 nm SRAM-based FPGA are performed.The generation mechanism of multiple-upset modes is analyzed on the layout.In addition,the circuit failures caused by irradiations are systematically studied,and the propagation law of the transient pulse induced by heavy ions in the circuit is analyzed by the circuit simulation.Based on the simulation,the experimental results are further analyzed and discussed.Furthermore,hardened circuits are designed and their anti-radiation effect is investigated.The main results are as follows:（1）The multiple-upset modes are strongly correlated with different sensitive-region arrangements in the device layout,which results in a ratio of more than 51.9%for the most prone multiple-upset mode.Meanwhile,the linear energy transfer（LET）and the irradiation angle of heavy ions can affect the generation mechanism of multiple upsets.⁷⁸Kr ions with low LET（～31.0 Me V/（mg/cm²））mainly cause multiple upsets in adjacent memory cells through the direct charge-collection process,while ¹²⁹Xe ions with high LET（～66.5 Me V/（mg/cm²））can induce more severe well-potential disturbance,resulting in serious parasitic bipolar effects,which leads to multiple upsets in interval memory cells.Additionally,it is found that compared to the vertical incidence into the well,heavy ions incident along the well can cause a stronger well-potential disturbance,resulting in a 5.7 times increase in the proportion of interval multiple upsets.（2）Compared to the heavier ¹²⁹Xe ions with an energy of 771 Me V,when ⁷⁸Kr ions reach an energy of 3348 Me V,they cause larger multiple upsets,indicating that when the LET of heavy ions exceeds the upset threshold of the nanoscale device,the heavy-ion energy can affect the scale of multiple upsets.GEANT4 simulation results show that this is due to the ⁷⁸Kr ions at 3348 Me V producing an electron-hole-pair spatial distribution that is 2 times wider than that of ¹²⁹Xe ions in the device,which is in good agreement with the experimental results.It is found that although both the angled and reduced-voltage irradiations induce a larger scale and a higher proportion of multiple upsets,the multiple-upset modes are correlated with the ion energy.Furthermore,it is found that the tilted irradiation causes the ion tracks to widen,for the nanoscale devices with non-uniform sensitive-region arrangements,leading to the significant orientation effects in multiple upsets,and the difference in the proportion of multiple upsets in two directions of the device reaches 33.3%.（3）D flip-flop（DFF）upsets caused by SET account for as high as 94.3%,and the cross-section of DFF upsets caused by SET generated by heavy ions at the clock buffer is approximately 15.0 times greater than the upset of DFF itself,indicating that SET is the main reason for the failure of nanoscale circuits.Besides,it is found that different circuit nodes within DFF cells have different sensitivities to SET,and circuit-simulation results show that this is due to the on-state metal-oxide-semiconductor transistor within DFF cells providing recovery current to the injected nodes.In addition,the failure of peripheral circuits causes up to 4753 DFF upsets,which severely impacts the entire circuit function.Hardened circuits are then designed,and the experimental results indicate that they can effectively reduce the failure probability caused by SET affecting the peripheral buffers and single heavy ions simultaneously affecting two redundant circuits.Compared with unhardened circuits,the cross-section of hardened circuits is reduced by one to two orders of magnitude.In addition,the experimental results show that due to the hardening design for the critical global resources in the system,the entire circuit can be immune to burst errors,thereby significantly improving the reliability of digital-circuit systems.For 28 nm SRAM-based FPGAs,this study establishes a general method for extracting multiple upsets that is suitable for the very-large-scale integrated circuit with unknown layout information.Then the detailed size and shape information of multiple upsets caused by heavy-ion irradiation is successfully obtained,and it is found that the direct charge-collection mechanism and the parasitic bipolar effects are the main reasons for various multiple-upset modes in the devices.In addition,experimental results reveal the correlation between different ionization-track structures of heavy ions with different parameters and multiple-upset modes.Furthermore,various modes and physical mechanisms of circuit failure caused by SET are clarified through experiments and circuit simulations.The experimental results of the hardened circuits show that the serious impact of SET can be effectively mitigated by adopting synchronous ports,triple modular redundancy,and by increasing the physical distance.The research results in this study provide fundamental data and theoretical support for the layout-level and circuit-level hardening designs for radiation-hardening devices.