Research And Implementation Of Memristor-based Complete Logic-Computing Hardware Primitives

In order to solve the "memory wall" and "power wall" issues brought by the separation of computing and storage unit in the von Neumann architecture,memristor-based logic computing brings new vitality.Many logic-in-memory computing methods have been developed,each with its own advantages and disadvantages,but there are still some problems.Overall,this research field is mainly focused on goals such as efficiency,cascading,and reconfigurability.Against this background,this work proposes an innovative class of V/R-R-type serial logic computation hardware primitives and their circuit configuration methods.This type adopts the advantages of both stateful and non-stateful logic,and effectively avoids the shortcomings of both to some extent.The primitive circuit achieves 16 complete Boolean logic functions in a fixed circuit topology by driving logic computation with conditional voltage and input state.This enables the implementation of multiple,non-monotonic logic computations,and the feasibility of the computation method is fully validated through simulation verification and electrical testing.In the first type of approach presented in this work,the logic primitive circuit structure consists of two parallel memristors and one load resistor(2M-1R).The two-input information are each mapped to the resistance state of the input memristor and the bias voltage of the control terminal.After the computation is completed,the result is stored in the output memristor,and based on mature read circuit resources,the signal conversion between resistance and voltage is achieved in the computation step without additional read operations,which facilitates the heterogeneous integration of the computing system.In the 2M-1R scheme,only one input information is saved as the resistance state of the memristor,and a circuit structure consisting of three parallel memristors and one load resistor(3M-1R)is further proposed to map the input information to the resistance state of two input memristors,and the result is also stored in the output memristor after one step of computation.Compared with stateful logic,both computation schemes have significant advantages in terms of delay and device counts,and any Boolean logic function can be implemented according to fixed delay parameters and device counts.Furthermore,the two primitive circuits are cascaded and mapped to the memristor-based crossbar array to complete one-bit adder function test,solving the cascading problem relative to non-stateful logic.Additionally,at the end of the computation,the input and output information are complete,reducing the computing module’s demand for data transmission bandwidth.The impact of multiple random parameter variables of hafnium oxide memristors on the calculation accuracy of the two proposed primitive circuits is theoretically analyzed.Under given device parameters,a Monte Carlo simulator is built to evaluate the calculation error probability of the logic primitive circuit with different input combination configurations.Furthermore,the maximum tolerance range of the primitive circuit to device parameter fluctuations is deduced to guide device optimization.Furthermore,with the help of new materials,hafnium oxide memristor used to demonstrate the computation method are optimized,and the consistency of device parameters is improved by modifying the electrodes with nano-metal particles.For the most easily calculated incorrect input combinations in the2M-1R type,experimental testing shows that the calculation accuracy of the primitive circuit is increased from 64.4% to 99% based on the optimized device,consistent with the theoretical analysis conclusion.This work maps primitive circuits onto the 1T1R array,and explores the parallelism of logical computations.Firstly,a multidimensional and detailed analysis is conducted on the adaptability of parameters between memristors and transistors.Secondly,by utilizing the gate voltage of transistors to correlate logical input operands,the computation scheme proposed in the array is parallelly laid out.A demonstration of bitwise parallel logical operation with four inputs is performed based on the T5830 testing platform.Efficient design schemes for one-bit full adder,N-bit adder,and N-bit comparator are proposed,expanding the application fields of logic-in-memory computing.Since complex operations are executed in the array,CMOSbased control components are required to determine the order of operations.In the final part of this work,a prototype conceptual design of peripheral control circuit simulation is presented.This thesis provides various complete hardware logical primitives and computing circuit supports for constructing memristor-based in-memory computing system.