Nueromorphic Computing Based On Memtransistors

Due to the mismatch between the growth rate of computing power demand in AI and the computer hardware size,the revolutionary change of traditional computer architecture is in urgently need.The neuromorphic computing inspired by biological neural network have realized in-memory computing architecture including artificial neuron and artificial synaptic circuit based on emerging neuromorphic devices,which provides an effective solution to break through the traditional"Von Neumann"architecture.This thesis investigates the fabrication process and neuromorphic characteristics of memtransistors based on the ultra-thin low-dimensional material.By utilizing the diverse synaptic plasticity of low-dimensional memtransistors,a complete spiking neural network（SNN）hardware architecture including neurons,synapses,and weight updating circuits is successfully designed.In addition,we designed and fabricated a phototransistor with memory characteristic,studied and measured its optoelectronic characteristics,and realized the SNN design with in-sensor computing architecture.The main research results are as follows:Firstly,a field-effect transistor with graphene as the channel and organic ferroelectric material PVDF as the gate dielectric was fabricated.By utilizing the zero-bandgap and bipolar characteristics of graphene and the non-volatile polarization state in the ferroelectric gate dielectric,the graphene channel can be configured into two different modes with reconfigurable hole or electron dominated transportation.Synaptic plasticity was measured in both modes:both modes have opposite synaptic plasticity and exhibit excellent linearity（α=1.3/-1.1）,ultra-low cycle-to-cycle variation（2%）and 5-bit conductance states.By designing the structure of complementary synapses with two transistors in two modes connected in parallel,the supervised learning algorithm Re Su Me in SNN is compactly implemented without the requiring of complex supervised learning circuits（synaptic area is 100μm²）.The simulation task with MNIST dataset was completed achieving 86%recognition accuracy and ultra-low power consumption of 8 p J per operation.Then,a multilayer SNN hardware architecture based on complementary synapses is designed with the ability to to handle nonlinear problems.The simulation of the classical nonlinear problem XOR is completed to verify the feasibility of the multilayer SNN designed in this thesis.Secondly,the complementary synapse performance is improved by replacing the zero-bandgap graphene channel with a WSe₂ channel having a certain bandgap and bipolarity.The on/off ratio of transistors is increased from 2 to 10⁶.Complementary synapse based on two parallel WSe₂ ferroelectric transistors are experimentally demonstrated:the ferroelectric material is locally polarized by two local top gates,and one of the channels is modulated to p-type and the other to n-type with electrostatic doping method.The R-STDP synaptic characteristics of this complementary synapse were designed and measured.The hardware implementation of the R-STDP characteristics based on the complementary synapse realize a more simplified hardware circuit than the reported design.A hardware implementation of reinforcement learning SNN is designed.The classical decision task of cart-pole problem is simulated to verify the feasibility of reinforcement learning SNN based on complementary synaptic devices.Thirdly,this thesis focuses on the implementation of SNN with in-sensor computing architecture.A phototransistor with memory characteristics is designed and fabricated.1)To improve the device sensing sensitivity,the transistor structure is changed from top gate to back gate,a split-gate structure is designed for the realization of PN or NP photodiode.2)With WSe₂ as the channel and Al₂O₃/Hf O₂/Al₂O₃ as the floating-gate dielectric,the WSe₂phototransistor shows photodiode characteristics by applying the reverse voltage to both gates.With the photovoltaic effect,the WSe₂ split-gate transistor spontaneously generates photocurrent.By controlling the amount of charge stored in the Hf O₂ layer,the WSe₂ split-gate transistor achieves non-volatile tunable photoresponsivity.Thus,a photodetector with sensing,computing and memory functions has been successfully realized.Further,the circuit structure of the pixel cell based on the WSe₂ split-gate transistor was designed with event-driven characteristics.The generated photocurrent of this pixel cell under different light intensities was measured,the adjustable event-driven characteristics were verified.The SNN based on the pixel unit is designed.The lane keeping and action recognition tasks is successfully simulated which reduces the amount of sensory data by 97%compared with conventional frame-rate cameras.An ultra-low temporal resolution of 20μs is achieved.