The Research On Van Der Waals Integration And De-integration Process Of Two-Dimensional Transistors

Two-dimensional materials have great potential for future applications in electronics and optoelectronics,and their development and opportunities have attracted tremendous interest.The technique of assembling them into van der Waals（vdW）heterostructures is essential for the fabrication of functional devices that are not limited by lattice matching and process compatibility.By vdW integration,the inherent interfaces of the materials can be preserved as well as the advantages of integrating each material,thus paving the way for the realization of high-performance devices.Benefiting from pioneering research over the past decade,vdW integration technique has grown considerably,providing a broad platform for fundamental research and novel device concepts.With the further research on vdW heterostructures,there is a growing need for more complex heterostructures,rather than simple combinations of 2D materials.However,the current state-of-the-art vdW integration technique can only perform unidirectional integration on the chip plane,which severely limits the application scope of vdW integration.Based on this,we first develop a vdW integration technique on a vertical plane,and use this method to realize ultra-high density vertical transistors.Then,in view of the fact that vdW heterostructures can only be integrated in unidirection,a vdW de-integration method is developed,and the de-integration of vdW heterostructures is experimentally achieved for the first time.Finally,using the developed vdW integration and de-integration techniques,the reconfiguration of high-performance functional devices and the fabrication of twisted-angle double-layer heterostructures with various angles are realized.The main contents of this thesis are as follows:（1）Developing a vdW integration method enables the fabrication of high-density transistors,logic devices and memory on vertical substrates.By using a custom-designed T-shape PDMS stamp,prefabricated planar transistors can be integrated onto vertical sidewalls,hence overcoming the incompatibility of planar processes with vertical structures.Owing to the low strain induced during dry-lamination process,the transistors could conformally contact to the vertical substrate without any damage or degradation,resulting in high-performance vertical transistors with low device-to-device variation.Based on this technique,60 MoS₂vertical transistors could be stacked within a small footprint of 0.035μm²,corresponding to a highest device density over 1.7×10¹¹cm^–2.Finally,we demonstrate two approaches for scalable fabrication of vertical transistor arrays,including the lamination onto multiple vertical substrates simultaneously,as well as on the same vertical substrate using layer-by-layer lamination techniques.Our study overcomes the incompatibility of planar fabrication processes with vertical substrates,but also breaks the limit of transistor integration density,opening up a new dimension for high-density vertical transistors and integrated circuits（2）Developing a vdW de-integration approach first achieves the disassembly of vdW heterostructures by using atomically flat polymers as substrates.The WSe₂and BN are disassembled and reassembled repeatedly on the same MoS₂,and the disassembled MoS₂exhibits the same clean surface as the initial state,indicating the reliability of vdW de-integration technique.Using this technique,the reconfigurations of transistor from n-type to p-type and from back gate to dual gate are achieved by restacking different contact metals and dielectrics on the same MoS₂flake.In addition,the high stability and reliability of the vdW de-integration and re-assembly techniques is further demonstrated electrically by multiple disassembly and reassembly of vdW metal electrodes on the same MoS₂flake.（3）Using vdW integration and de-integration techniques,reconfigurable high-performance functional devices and the preparation of vdW heterostructures with various torsion angles have been realized.A floating-gate memory based on four-layer vdW heterostructures（graphene/BN/MoS₂/metal）achieves non-volatile characteristics with long-term retention,low power consumption,and high current switching ratio,owing to ultra-thin heterostructure,ultra-fast carrier transport speed and high carrier concentration tunability.Through vdW de-integration and reassembly techniques,the memory can be successfully disassembled and reassembled in a different sequence,enabling reconfigurable behavior where the device functions as a Schottky diode.Finally,a vdW heterostructure can be assembled and reassembled multiple times at arbitrary angles after disassembly and rotation is demonstrated,and highly switchable anisotropic Raman behavior is observed.The twisted-angle bilayer materials with different angles fabricated by this method use the same materials to ensure that different samples have the same interface conditions and material qualities,which provides convenience for the study of twisted-angle bilayer systems with different angles.