Research On New Structures Of SiC MOSFET Devices With High-performance And High-Reliability

The third-generation wide band-gap semiconductor material,represented by silicon carbide（SiC）,is the ideal power semiconductor material for high temperature,high frequency,and radiation resistant applications.SiC Metal-Oxide-Semiconductor Field-Effect Transistor（MOSFET）demonstrates superior performances including low loss,high switching speed,high junction temperature and so on,which is accelerating the reform of power electronics equipment,for higher power density,higher efficiency,harsher environment.SiC MOSFETs are widely used in power electric applications and have a promising future.Compared with the mature Si-based power devices,however,SiC devices are still in the preliminary stage of research and development.Additionally,several reliability-relate issues caused by intrinsic material pose extreme challenges to the fabrication process and device design.Therefore,it is essential to explore and develop high-performance and high-reliability SiC MOSFET devices for improving the trade-off relationship between electrical performance and reliability of SiC MOSFETs.Based on the theories of power semiconductor devices and the reliability enhancement mechanisms of SiC MOSFETs,this thesis seeks breakthroughs in the field of device design and new structures with high-performance and high-reliability.For this research topic,three new structures for planar-gate SiC MOSFETs and one new structure for trench-gate SiC MOSFET are proposed and verified by simulations and experiments.（1）Aiming at the difficulty in the synergistic improvement of high-frequency performance and gate oxide reliability for conventional split planar-gate SiC MOSFET,a novel split planar-gate SiC MOSFET structure with source field plate（SFP-SG-MOSFET）is proposed.The proposed SFP-SG-MOSFET features a source metal layer embedded between two adjacent split poly-Si gates,modulating the local electric field at the edge of split-gate corner.And a high-quality field interlayer dielectric（ILD）layer with relatively large value of permittivity is sandwiched between the source metal layer and the semiconductor layer for reducing electric field at the interface.When blocking voltage is 1.2 k V,the maximum oxide electric field is decreased from 7.2 MV/cm to less than 3.0 MV/cm.Meanwhile,the new structure retains the benefits of the conventional split planar-gate SiC MOSFET for high-frequency applications.Compared to the conventional planar-gate SiC MOSFET,the new structure offers an 18.7%reduction in total switching losses,in particular,a 57%reduction in turn-off loss.Consequently,a fabrication process flow and a layout are designed for the 1.2 k V SFP-SG-MOSFET with domestic manufacturing technology.The experimental results show that the blocking voltage of the SFP-SG-MOSFET is improved to 1377 V with 3.71 mΩ·cm²of specific on-resistance.The FOM[R_ON×C_rss0V]is 14528 mΩ·p F,FOM[R_ON×C_rss1000V]is 293 mΩ·p F,which are82%and 58%less than that of the conventional planar-gate SiC MOSFET,respectively.（2）Aiming at the difficulty in the synergistic improvement of first-quadrant and third-quadrant characteristics,a novel SiC MOSFET structure with integrated freewheeling diode（FWD-MOSFET）is proposed.The new structure utilizes the N-Poly Si/N-SiC heterojunction diode with low turn-on knee voltage,which improves the performance of body diode.According to the principle of alternating first-quadrant and third-quadrant conduction,a N-Poly Si/N-SiC heterojunction diode is embedded above JFET region,which enables the JFET region shared in both conduction modes.Therefore,forward voltage in the third quadrant,reverse recovery charge,reverse recovery time for the new structure is reduced by 50%,73%and 40%,respectively,compared with that of the conventional planar-gate SiC MOSFET.And the new structure still retains good basic MOSFET performance.Consequently,two types 1.2k V SiC MOSFETs with integrated Schottky barrier diode are designed and fabricated.The experimental results show that the new device has a forward voltage of 1.39 V in the third quadrant(@I_sd=2 A,V_gs=-5 V),a 72%reduction compared to a conventional planar-gate SiC MOSFET.（3）Aiming at the poor ruggedness and short-circuit withstanding time in the conventional planar-gate SiC MOSFET,the short-circuit experiments and simulations are carried out to studying the short-circuit failure phenomena and mechanisms for commercial 1.2 k V planar-gate SiC MOSFET.It is demonstrated that reducing saturation current could improve the short-circuit withstanding time.Then a novel structure is proposed,which integrates a self-pinching structure.The self-pinching structure features that an N-type current spread layer is sandwiched between the P+layer and the buried P-shield layer.The forward current path can be self-adjusted at various drain-source voltages.Under low drain-source voltage,the new structure offers a good conduction capability.Under high drain-source voltage,the JFET structure self-pinches off,and limits the saturation current of the device,reduced by 60%.Additionally,both the shallow P+layer and the buried P-shield layer collaboratively shield the Schottky contact and the SiC/Si O₂ interface from a high electric field.The design concept alleviates the trade-off relationship between short-circuit withstanding time and specific on-resistance.The new structure offers a short-circuit withstanding time of 13μs,roughly 2.6×longer than that of the conventional planar-gate SiC MOSFET.Meanwhile,the electric field of the SiC/SiO₂ interface is reduced by 76%.（4）Aiming at the difficulty in the synergistic improvement of specific on-resistance and short-circuit withstanding time for trench-gate MOSFET,a novel trench SiC MOSFET structure with dual gate（DG-TMOS）is proposed.Based the theory and simulation analyses,the effects of P-shield layer on specific on-resistance,blocking voltage,capacitance,gate-charge,and dynamic switching characteristics for a conventional trench SiC MOSFET.It is revealed that the floating P-shield state facilitates the improvement of the specific on-resistance,and the grounded P-shield state facilitates the improvement of the switching characteristics.Therefore,the new design concept is proposed,which optionally controls the electrical connections of the P-shield layer under the trench.Only in the conduction condition,the P-shield layer is floated to reduce the extension of the depletion region of P-shield layer/N-drift and increase the width of current conduction path.In addition,in short-circuit condition,the saturation current can be remarkably reduced for the same active area,due to a large cell dimension of the new structure.Hence,the short-circuit capability of the new structure is improved.The new structure offers a short-circuit withstanding time of 10μs,increased by 0.92%.Compared with the conventional trench MOSFET,the turn-on loss and turn-off loss of the new structure are reduced by 32%and 48%.