Research On Key Technologies Of Highly Reconfigurable RF-to-Bits Transceiver

In recent years,with the rapid development of multi-standard broadband wireless communication and multi-band cognitive electronic warfare,RF transceivers known as the‘pearl’ of communication systems need to achieve fully integrated,low-power,multidimensional reconfigurable and other characteristics.Among them,the Sub-6 GHz band transceiver is the most widely used and has always been a hot topic in various fields of the world.In addition,with the development of software defined radio(SDR)technology,the RF sampling analog-to-digital converter(ADC)used in the next generation of RF direct acquisition receivers is also the focus of current research.In this dissertation,the reconfigurable RF-analog integrated transceiver front-end chip,the reconfigurable RF digital integrated transceiver System on Chip(SoC)and the RF sampling ADC chip are taken as the research objects.Through the deep theoretical analysis of the architecture and key circuit modules,the design,tape-out and packaging test verification of various chips are completed.The main research work and innovation are as follows:First,aiming at the problems of Sub-6 GHz band congestion and signal blocking,this dissertation chooses the zero-IF transceiver structure.For the receiving link,an “AttenuatorFirst” broadband reconfigurable current-mode receiving front-end architecture based on the“Mixer-First” structure is proposed,which simplifies link matching and greatly improves the dynamic range and linearity.In practical applications,an off-chip high-efficiency heterogeneous low-noise amplifier(LNA)can be selected to meet different communication standards.Firstly,an improved 8-bit fractional step attenuator based on π-type is proposed.The whole is composed of 8 groups of binary weight attenuation units in parallel,which can reduce the insertion loss and improve the design freedom.The gain adjustment range is > 40 d B,and the minimum gain adjustment step is < 0.5 d B;secondly,a high-linearity orthogonal double-balanced passive mixer is used to realize down-mixing and frequency impedance transfer,and increase blocking suppression.The baseband part is composed of a reconfigurable first-order low-pass filter(LPF)based on a transimpedance amplifier(TIA)cascaded with a first-order LPF to achieve an adjustable signal bandwidth of 8-200 MHz and suppression of mixing spurs.Second,A reconfigurable transmitter front-end architecture based on current-mode input upmixer is proposed.The baseband input includes a passive LC reconfigurable notch filter to suppress the sampling image of the digital-to-analog converter(DAC)and an active secondorder Butterworth reconfigurable LPF with tunable signal bandwidth,both of which are based on 65 nm CMOS process design and tape-out verification,respectively.The test results show that the notch filter achieves a 384-468 MHz signal bandwidth tuning range and a 750MHz-1.01 GHz notch position adjustable;the second-order LPF achieves bandwidth coverage of 8-200 MHz,corresponding to a spurious-free dynamic range(SFDR)of 57.7-72.3 d B.A gain-reconfigurable dual-balanced active mixer based on current input is proposed.A current mirror based on op-amp clamping is used to achieve a high linear conversion of baseband filter output voltage to current,and its image is used as the input of the active mixer.The overall gain adjustment range of 36 d B and the minimum step of 0.05 d B are achieved.Finally,based on the 65 nm CMOS process,a reconfigurable RF-analog integrated transceiver front-end chip is designed and implemented.The chip area is 2786μm*2632 μm,and the overall power consumption is 437 m W.The vector network and spectrum analyzer test results show that the working frequency band covers 75 MHz-6 GHz with the bandwidth of 8-200 MHz coverage,the receiving link achieves > 40 d B attenuation range,as well as a noise figure of 12 d B in the unattenuated state,and in the 3 GHz band under the input third-order intermodulation point of 7 d Bm or so,compared with the traditional voltage-mode LNA receivers to greatly improve the linearity of the receiver;The transmitter link realizes a gain adjustment range of >30 d B and a high input third-order intermodulation point of 16.08 d Bm at 3 GHz,which lays the foundation for the front-end implementation of the subsequent RF-digital integrated transceiver SoC chip with a higher degree of integration.Third,Based on the research and test of the reconfigurable RF-analog transceiver front-end chip in the early stage,in view of the international deployment of 5G communication applications in the frequency band near 6.5 GHz,the fractional frequency division phaselocked loop,digital baseband ADC、DAC and partial calibration circuit and high-speed serial communication Ser Des interface are further integrated,and extended to 2 receiving and 2transmitting channels.Firstly,a calibration circuit structure based on 10-bit adjustable current compensation is proposed to optimize the local oscillator phase delay and compensate the leakage of the transmitter mixing output unit.Secondly,the structure and key circuits of four-channel 1 GS/s,14-bit segmented current steering DAC and four-channel500 MS/s,14-bit pipelined ADC applied to digital baseband are introduced.Finally,based on the 65 nm CMOS process,a reconfigurable RF-digital integrated transceiver SoC chip was designed and implemented.The bare chip area is 8 mm*6 mm,and the advanced FCBGA(Flip-Chip-Ball Grid Array)package is used to improve performance and efficiency.The 6-layer substrate is used for placement and routing.The SoC chip is tested by a spectrum analyzer,and the overall power consumption is 2.207 W.Compared with the previous version of the transceiver front-end chip,the operating frequency is extended from 75 MHz-6 GHz to 75 MHz-6.5 GHz.The LO leakage is increased by more than 20 d B below the working frequency band of 6 GHz and 10 d B above 6 GHz.The overall image suppression and third harmonic suppression are stable at more than 60 d B.Finally,the performance of the whole SoC chip is summarized and compared with the related SoC chips published in the top journals and conferences in recent years.It has certain advantages in working frequency band and bandwidth,gain adjustment range and receiver input third-order intermodulation point.Fourth,the RF sampling ADC chip in software radio application is studied.Using the advantages of advanced nano-technology,a single-channel 1 GS/s,12-bit mixed-domain pipelined ADC and a 16-channel time-domain interleaved 5-20 GS/s,10-8 bit reconfigurable time-domain ADC architecture are proposed respectively.The key circuits and module innovations are analyzed.Finally,the two chips are tested and verified based on 28 nm and40nm CMOS processes,and compared with ADC chips with similar indicators at home and abroad in recent years.The two chips achieve a better Figure of Merit of 22.1 f J/ conv-step and 58.9 f J/ conv-step(10-GS/s mode)in terms of energy efficiency ratio,respectively,which can effectively support the research of subsequent RF direct acquisition receivers and continue to work towards the final software radio platform.