Research On The Key Techniques Of Medium-to-high Speed Successive-approximation Analog-to-digital Converters

Analog-to-digital converter（ADC）converts continuous analog signals into discrete digital signals,which is an integral part of various electronic equipment systems.In recent years,the mobile communication terminal industry has developed rapidly,and the demand for medium-to-high-speed low-power ADC increases.Due to the rapid progress of semiconductor technology,the increased characteristic frequency and reduced power consumption of transistors provide more design space for medium-high speed and low-power analog-to-digital converters.Successive Approximation Register（SAR）ADC has the advantage of power consumption.In SAR ADC,the proportion of analog circuits is small and the proportion of digital circuits is large,which is suitable in the application of the reduced supply voltage.In advanced technology,SAR ADCs and Pipelined-SAR ADCs are widely employed to realize high-speed,medium-to-high-resolution converters.Meanwhile,time-interleaving is often applied to single-channel SAR ADC.In deep sub-micron process,it is valuable to further optimize the speed,accuracy,and power consumption of a single-channel SAR ADC.The research of the key technologies of high-speed,medium-high-precision,and low-power SAR ADCs is of great significance.Firstly,the capacitor switching scheme for high-speed SAR ADC is studied.In this dissertation,an improved switchback DAC capacitor switching scheme is proposed based on the analysis of the capacitor switching power consumption and the comparator input common mode voltage.Compared with other capacitor switching schemes,the proposed improved switchback capacitor switching scheme is more suitable for high-speed SAR ADC.In addition,compared with the conventional switchback switching scheme,the power dissipation of the improved switchback capacitor switching scheme does not increase.A 160MS/s 12bit SAR ADC is fabricated in 40nm CMOS technology based on the improved switchback switching scheme.The experimental result shows that an SNDR of 62.1d B and an SFDR of 81.61d B are achieved with a 7.5MHz input frequency at 160MS/s.Meanwhile,an SNDR of 57.18d B and an SFDR of 75.29d B are achieved with a 79.9MHz input frequency at 160MS/s.Based on the performance of the above-mentioned 160MS/s 12bit SAR ADC,some calibration schemes are adopted to improve the accuracy of the SAR ADC.The parasitic capacitance effect calibration scheme of the SAR ADC with bridge capacitor is proposed based on the existing parasitic capacitance calibration scheme.The bridge capacitor is set to 2C₀,which provide redundancy for the overall LSB-side capacitor.A binary weighted capacitor array is used to compensated the weight error caused by parasitic capacitance.The weight error caused by parasitic capacitance in LSB-side is eliminated by comparing the weight difference between the high and low capacitances.In addition,a comparator offset cancellation technique based on charge pump is proposed to ensure the calibration accuracy.Compared with the existing parasitic capacitance calibration scheme,all the DAC capacitors in the proposed calibration scheme are integer multiples of unit capacitor,which can achieve better matching.Due to the process deviation,the actual capacitance value of the DAC capacitor array often deviates from the ideal value.The capacitor mismatch error will deteriorate the linearity of the whole converter.To further improved the accuracy of the medium-to-high speed SAR ADCs,a genetic-algorithm-based（GA-based）SAR ADC capacitor mismatch calibration scheme is proposed.The nonbinary-weighted SAR ADC is adopted to provide the redundancy to tolerate the capacitor mismatch error.Meanwhile,the weight error caused by capacitor mismatch is extracted by the GA-based algorithm.Instead of adopting PN injection and LMS algorithm,the GA-based calibration scheme is a foreground digital calibration scheme and no extra dither is added.To verify the effectiveness of the calibration algorithm,a 12bit nonbinary weighted SAR ADC was designed based on 40nm CMOS technology and the related simulations are performed based on transistor-level schematic.The proposed calibration scheme is verified based on the data obtained from the schematic simulation.As can be seen from the simulation results,after GA-based calibration scheme,INL decreases from+2.22/-2.12LSB to+0.81/-0.80LSB,and DNL decreases from+1.79/-1.00LSB to+0.99/-1.00LSB.The simulation results show that the proposed GA-based calibration scheme can effectively improve the linearity deterioration caused by capacitance mismatch.Because of the successive approximation algorithm,SAR ADCs with traditional structures have little advantage in conversion rate.Therefore,the techniques of 2b/cycle SAR ADC are studied in this thesis.In 2b/cycle SAR ADC,2bits are converted in each bit cycle,which can improve the conversion rate of SAR ADC.In this design,an interpolating 2b/cycle SAR ADC architecture is proposed.Two sets of DAC capacitor arrays are reused to generate three sets of differential residual signals.Three comparison results are generated by comparing three sets of differential residual signals.By reusing DAC capacitor arrays to generate interpolated comparison levels,the high-speed 2b/cycle SAR ADC architecture is realized,with no additional reference-level-generating DAC arrays,which saves power consumption and area.The prototype is fabricated in 180nm CMOS technology.The experimental result shows that an SNDR of 49.76d B and an SFDR of 60.64d B are achieved with a 1.8MHz input frequency at80MS/s.Meanwhile,an SNDR of 45.82d B and an SFDR of 58.57d B are achieved with a39.9MHz input frequency at 80MS/s.