Research On High-Dynamic Receiver

GNSS(Global navigation satellite system) receiver is widely used in military field,as a result, research on high-dynamic technology of GNSS receiver is gaining increasing concern.In this paper, critical technologies of high-dynamic GNSS receiver have been designed and implemented.The theis includes:1. several acquisition algorithms were proposed.The "Multi-bank+ fft" based method can search in both time-domain and frequency-domain,which means it can locate thecode phase and doppler frequency parallelly.Thereforce,it is the fastest algorithm that is applied to high-dynamic acquisition. On the other hand, folded-match filter and PPT-match filter are adopted for FPGA design of the match filter, resulting in a large reduction of FPGA reources.2. For code tracking algorithm, a MATLAB simulation and design of the carrier assistant technology and the delay-lock-loop method are completed.Also a carrier-loop composed of a CPAFC and Costas for high dynamic application have been designed and implemented. 3. Three methods of bit synchronization has been introduced and compared with each other. An improved histogram bit synchronization method and a self-adaptive maximum likelihood bit synchronization method were proposed.4. An engineering design of high-dynamic GNSS receiver has been proposed.The design include hardware, FPGA and DSP architecture. A detailed introduction of some important DSP modules has been made.